Arthur Heymans uploaded patch set #2 to this change.

View Change

[NEEDSTEST]cpu/amd/family16: Use parallel mp init

This now computes an MTRR solution based on coreboots allocation and
always uses that solution over the one set by AGESA.
Syncing MSR is now done in sipi_vector.S.

Change-Id: If3326c5fbd278f8f974d5408e16440e3b56b1b44
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/northbridge/amd/agesa/family16kb/Kconfig
M src/northbridge/amd/agesa/family16kb/northbridge.c
3 files changed, 30 insertions(+), 168 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/64496/2

To view, visit change 64496. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If3326c5fbd278f8f974d5408e16440e3b56b1b44
Gerrit-Change-Number: 64496
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@mailbox.org>
Gerrit-MessageType: newpatchset