Subrata Banik uploaded patch set #2 to this change.

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The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)

soc/intel/cmn/graphics: Use DSM size for calculating GTT offset

This patch overrides the assumption being made by the GFX PEIM blob
between version 1029 and 103x to fix some issue where GTT offset
has calculated based on the eDP panel resoultion rather relying on
the pre-allocated memory limit for IGD.

Now this is causing major blocker for CrOS as GFX PEIM latest version
is no more working with existing OS (causing reboot or blank display).

To fix this issue, coreboot tries to perform an override to restore
PANEL_SURF register to the original value which has calculated based
on pre-allocated memory limit (B0/D0/F0:R 0x50 aka GGC) size.

BUG=b:314887266
TEST=Able to boot to OS where display is functional with latest FSP
(w/ GFX PEIM 1035).

Change-Id: Ied5af0faad73d0c88cab70dee6fe731f1a14653b
Signed-off-by: Subrata Banik <subratabanik@google.com>
---
M src/drivers/intel/gma/i915.h
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/80405/2

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