Hung-Te Lin submitted this change.
soc/mediatek/mt8192: Init DPM
DPM is a hardware module for DRAM power management and for better
power saving in low power mode.
BUG=none
TEST=Boots correctly on Asurada
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/dpm.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/dpm.h
6 files changed, 119 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c
index 0701c67..32bd407 100644
--- a/src/mainboard/google/asurada/mainboard.c
+++ b/src/mainboard/google/asurada/mainboard.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/mmio.h>
+#include <soc/dpm.h>
#include <soc/gpio.h>
#include <soc/regulator.h>
#include <soc/spm.h>
@@ -109,6 +110,9 @@
register_reset_to_bl31();
+ if (dpm_init())
+ printk(BIOS_ERR, "dpm init fail, system can't do DVFS switch\n");
+
if (spm_init())
printk(BIOS_ERR, "spm init fail, system suspend may stuck\n");
}
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig
index 36ad2e3..67e5a52 100644
--- a/src/soc/mediatek/mt8192/Kconfig
+++ b/src/soc/mediatek/mt8192/Kconfig
@@ -45,6 +45,18 @@
This option enables memory basic compare test to verify the DRAM read
or write is as expected.
+config DPM_DM_FIRMWARE
+ string
+ default "dpm.dm"
+ help
+ The file name of the MediaTek DPM DM firmware
+
+config DPM_PM_FIRMWARE
+ string
+ default "dpm.pm"
+ help
+ The file name of the MediaTek DPM PM firmware
+
config MCUPM_FIRMWARE
string
default "mcupm.bin"
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 2fc8f39..c02eabc 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -35,6 +35,7 @@
romstage-y += mt6359p.c
ramstage-y += ../common/auxadc.c
+ramstage-y += dpm.c
ramstage-y += flash_controller.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += emi.c
@@ -52,6 +53,8 @@
MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192
mcu-firmware-files := \
+ $(CONFIG_DPM_DM_FIRMWARE) \
+ $(CONFIG_DPM_PM_FIRMWARE) \
$(CONFIG_MCUPM_FIRMWARE) \
$(CONFIG_SPM_FIRMWARE)
diff --git a/src/soc/mediatek/mt8192/dpm.c b/src/soc/mediatek/mt8192/dpm.c
new file mode 100644
index 0000000..7acdf68
--- /dev/null
+++ b/src/soc/mediatek/mt8192/dpm.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/dpm.h>
+#include <soc/mcu_common.h>
+#include <soc/symbols.h>
+
+static void reset_dpm(struct mtk_mcu *mcu)
+{
+ /* write bootargs */
+ write32(&mtk_dpm->twam_window_len, 0x0);
+ write32(&mtk_dpm->twam_mon_type, 0x0);
+
+ /* free RST */
+ setbits32(&mtk_dpm->sw_rstn, DPM_SW_RSTN_RESET);
+}
+
+static struct mtk_mcu dpm_mcu[] = {
+ {
+ .firmware_name = CONFIG_DPM_DM_FIRMWARE,
+ .run_address = (void *)DPM_DM_SRAM_BASE,
+ },
+ {
+ .firmware_name = CONFIG_DPM_PM_FIRMWARE,
+ .run_address = (void *)DPM_PM_SRAM_BASE,
+ .reset = reset_dpm,
+ },
+};
+
+int dpm_init(void)
+{
+ int i;
+ struct mtk_mcu *dpm;
+
+ /* config DPM SRAM layout */
+ clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1);
+
+ for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) {
+ dpm = &dpm_mcu[i];
+ dpm->load_buffer = _dram_dma;
+ dpm->buffer_size = REGION_SIZE(dram_dma);
+ if (mtk_init_mcu(dpm))
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index c68403b..2e8ac9e 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -27,6 +27,9 @@
PMIF_SPMI_BASE = IO_PHYS + 0x00027000,
PMICSPI_MST_BASE = IO_PHYS + 0x00028000,
SPMI_MST_BASE = IO_PHYS + 0x00029000,
+ DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000,
+ DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000,
+ DPM_CFG_BASE = IO_PHYS + 0x00940000,
AUXADC_BASE = IO_PHYS + 0x01001000,
UART0_BASE = IO_PHYS + 0x01002000,
SPI0_BASE = IO_PHYS + 0x0100A000,
diff --git a/src/soc/mediatek/mt8192/include/soc/dpm.h b/src/soc/mediatek/mt8192/include/soc/dpm.h
new file mode 100644
index 0000000..f5e704b
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/dpm.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_DPM_H__
+#define __SOC_MEDIATEK_MT8192_DPM_H__
+
+#include <soc/addressmap.h>
+#include <stdint.h>
+#include <types.h>
+
+struct dpm_regs {
+ u32 sw_rstn;
+ u32 rsvd_0[3072];
+ u32 mclk_div;
+ u32 rsvd_1[3071];
+ u32 twam_window_len;
+ u32 twam_mon_type;
+ u32 rsvd_2[1022];
+ u32 low_power_cfg_0;
+ u32 low_power_cfg_1;
+ u32 rsvd_3[1];
+ u32 fsm_out_ctrl_0;
+ u32 rsvd_4[8];
+ u32 fsm_cfg_1;
+ u32 low_power_cfg_3;
+ u32 dfd_dbug_0;
+ u32 rsvd_5[28];
+ u32 status_4;
+};
+
+check_member(dpm_regs, mclk_div, 0x3004);
+check_member(dpm_regs, twam_window_len, 0x6004);
+check_member(dpm_regs, low_power_cfg_0, 0x7004);
+check_member(dpm_regs, low_power_cfg_1, 0x7008);
+check_member(dpm_regs, fsm_out_ctrl_0, 0x7010);
+check_member(dpm_regs, fsm_cfg_1, 0x7034);
+check_member(dpm_regs, low_power_cfg_3, 0x7038);
+check_member(dpm_regs, dfd_dbug_0, 0x703C);
+check_member(dpm_regs, status_4, 0x70B0);
+
+#define DPM_SW_RSTN_RESET BIT(0)
+#define DPM_MEM_RATIO_OFFSET 28
+#define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET)
+#define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET)
+
+static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE;
+
+int dpm_init(void);
+
+#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */
To view, visit change 46393. To unsubscribe, or for help writing mail filters, visit settings.