Srinidhi N Kaushik has uploaded this change for review.

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soc/intel/tigerlake: Enable Audio on TGL

Configure UPD's to support Audio enablement.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 29d75f1..a1af2da 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -30,6 +30,10 @@
 #include <soc/serialio.h>
 #include <soc/usb.h>
 
+#define MAX_HD_AUDIO_DMIC_LINKS 2
+#define MAX_HD_AUDIO_SNDW_LINKS 4
+#define MAX_HD_AUDIO_SSP_LINKS  6
+
 struct soc_intel_tigerlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -115,6 +119,16 @@
 	uint8_t SataPortsEnable[8];
 	uint8_t SataPortsDevSlp[8];
 
+	/* Audio related */
+	uint8_t PchHdaDspEnable;
+	uint8_t PchHdaAudioLinkHdaEnable;
+	uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
+	uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
+	uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
+	uint8_t PchHdaIDispLinkTmode;
+	uint8_t PchHdaIDispLinkFrequency;
+	uint8_t PchHdaIDispCodecDisconnect;
+	
 	/* PCIe Root Ports */
 	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to Pcie devices.
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 4c309dd..41d0fd1 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -21,6 +21,7 @@
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <string.h>
 
 /* Debug interface flag */
 enum debug_interface_flag {
@@ -108,6 +109,19 @@
         m_cfg->ECT = 0; /* Early Command Training Enabled */
         m_cfg->RefClk = 0; /* Auto Select CLK freq */
 
+	/* Audio: HDAUDIO_LINK_MODE_I2S_SSP */
+	m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
+	m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
+	memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
+				sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
+	memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
+				sizeof(m_cfg->PchHdaAudioLinkSspEnable));				
+	memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,			
+				sizeof(m_cfg->PchHdaAudioLinkSndwEnable));	
+	m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
+	m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
+	m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
+
 	m_cfg->PchHdaAudioLinkDmicClkAPinMux[0]        = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6;
 	m_cfg->PchHdaAudioLinkDmicClkBPinMux[0]        = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2;
 	m_cfg->PchHdaAudioLinkDmicDataPinMux[0]        = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7;

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