Patrick Rudolph has uploaded this change for review.
Documentation: Document PMH known registers
Document what is known of Lenovo's PMH.
Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/pmh.md
2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
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--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -54,6 +54,7 @@
- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
- [T4xx common](lenovo/t4xx_series.md)
- [X2xx common](lenovo/x2xx_series.md)
+- [PMH](lenovo/pmh.md)
### Sandy Bridge series
diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md
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@@ -0,0 +1,69 @@
+# Lenovo's Power Management Hub
+
+The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC
+to controll power rails and reset lines on the lenovo mainboard.
+Starting with Ivy Bridge series, the CPLD was removed and an EC with higher
+pincount does the same job. The IO space to configure the PMH is still
+the same.
+
+## PMH access
+
+The PMH register can be accessed using the IO region:
+
+ IO region address: 0x15e0
+ IO region size: 16
+
+The IO region has the following layout:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Offset | Register function |
++-------------------+---------------------------------------+
+| 0xc | ADDR_L: Low address into PMH space |
++-------------------+---------------------------------------+
+| 0xd | ADDR_H: High address into PMH space |
++-------------------+---------------------------------------+
+| 0xe | DATA: The data to read/write in PMH |
++-------------------+---------------------------------------+
+```
+
+The PMH register space allows to access 512bytes.
+The following registers are known:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Offset | Register function |
++-------------------+---------------------------------------+
+| 0x50 | BIT3: dGPU power enable |
+| +---------------------------------------+
+| | BIT5: Backlight enable |
+| +---------------------------------------+
+| | BIT7: dGPU !reset |
++-------------------+---------------------------------------+
+| 0x51 | BIT0: Trackpoint enable |
+| +---------------------------------------+
+| | BIT2: Touchpad enable |
++-------------------+---------------------------------------+
+| 0x60 | BIT3: Dock event enable |
++-------------------+---------------------------------------+
+| 0x62 | BIT0: Ultrabay power enable |
++-------------------+---------------------------------------+
+| 0xc2 | ID: ID of PMH |
++-------------------+---------------------------------------+
+| 0xc3 | REV: Revision of PMH |
++-------------------+---------------------------------------+
+```
+
+The revision at 0xc3 seems to increment over time:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Revision | Mainboard generation |
++-------------------+---------------------------------------+
+| 4 | T520 and T420s |
++-------------------+---------------------------------------+
+| 5 | W530 |
++-------------------+---------------------------------------+
+| 6 | T470p |
++-------------------+---------------------------------------+
+```
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