Shelley Chen submitted this change.
mb/google/brox: Initialize TCHSCR_RST_L to 0
TCHSCR_RST_L signal was originally being configured to 1 in gpio.c but
this was causing some leakage. Configuring it to 0 initially in
romstage fixes this. Also, make sure that EN_PP3300_TCHSCR is
initialized in romstage as well.
BUG=b:322249892
BRANCH=None
TEST=Make brox boots and touchscreen is still working
Change-Id: I5bf1901a3a40a38237b950abcb758f96aebcc1cf
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80300
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 3f39f18..1464820 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -428,8 +428,12 @@
PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
+ /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
+ PAD_CFG_GPO(GPP_F7, 1, PLTRST),
/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_F9, 1, DEEP),
+ /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
+ PAD_CFG_GPO(GPP_F17, 0, DEEP),
/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
};
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