Sergey Larin has uploaded this change for review.
src/mainboard: Port for Chuwi Minibook (m3/8GB)
Hardware:
- Intel Core m3-8100Y (Amber Lake aka Kabylake)
- Sunrise Point-LP C iHDCP 2.2 Premium
- ITE IT8987E EC
- Unknown soldered 8GB memory - SPD was extracted from BIOS image
(BIOS says it's Micron/2 ranks/13-15-15-34)
- 1200x1920 eDP display (yep it's rotated)
- mini-HDMI port
- 1 USB 3.0, 1 USB 2.0, 1 USB Type-C port (as charger but working)
- eMMC storage (unknown)
- SD card slot
- M.2 2242 slot
- Intel WiFi chip
Currently hangs after postcar stage.
Change-Id: I7cfa4588802b9c07b504f03471265574608519c8
---
M src/drivers/spi/flashconsole.c
A src/mainboard/chuwi/Kconfig
A src/mainboard/chuwi/Kconfig.name
A src/mainboard/chuwi/minibook/Kconfig
A src/mainboard/chuwi/minibook/Kconfig.name
A src/mainboard/chuwi/minibook/Makefile.inc
A src/mainboard/chuwi/minibook/acpi/ec.asl
A src/mainboard/chuwi/minibook/acpi/mainboard.asl
A src/mainboard/chuwi/minibook/acpi/superio.asl
A src/mainboard/chuwi/minibook/acpi_tables.c
A src/mainboard/chuwi/minibook/board_info.txt
A src/mainboard/chuwi/minibook/data.vbt
A src/mainboard/chuwi/minibook/devicetree.cb
A src/mainboard/chuwi/minibook/dsdt.asl
A src/mainboard/chuwi/minibook/gma-mainboard.ads
A src/mainboard/chuwi/minibook/gpio.h
A src/mainboard/chuwi/minibook/hda_verb.c
A src/mainboard/chuwi/minibook/mainboard.c
A src/mainboard/chuwi/minibook/ramstage.c
A src/mainboard/chuwi/minibook/romstage.c
A src/mainboard/chuwi/minibook/spd/Makefile.inc
A src/mainboard/chuwi/minibook/spd/micron.spd.hex
A src/mainboard/chuwi/minibook/spd/spd.h
A src/mainboard/chuwi/minibook/spd/spd_util.c
A src/superio/ite/it8987e/Kconfig
A src/superio/ite/it8987e/Makefile.inc
A src/superio/ite/it8987e/it8987e.h
A src/superio/ite/it8987e/superio.c
28 files changed, 1,360 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38249/1
diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c
index 80c63e0..149a84e 100644
--- a/src/drivers/spi/flashconsole.c
+++ b/src/drivers/spi/flashconsole.c
@@ -22,11 +22,11 @@
#define LINE_BUFFER_SIZE 128
#define READ_BUFFER_SIZE 0x100
-static const struct region_device *rdev_ptr;
-static struct region_device rdev;
-static uint8_t line_buffer[LINE_BUFFER_SIZE];
-static size_t offset;
-static size_t line_offset;
+static const struct region_device *g_rdev_ptr;
+static struct region_device g_rdev;
+static uint8_t g_line_buffer[LINE_BUFFER_SIZE];
+static size_t g_offset;
+static size_t g_line_offset;
void flashconsole_init(void)
{
@@ -36,11 +36,11 @@
size_t len = READ_BUFFER_SIZE;
size_t i;
- if (fmap_locate_area_as_rdev_rw("CONSOLE", &rdev)) {
+ if (fmap_locate_area_as_rdev_rw("CONSOLE", &g_rdev)) {
printk(BIOS_INFO, "Can't find 'CONSOLE' area in FMAP\n");
return;
}
- size = region_device_sz(&rdev);
+ size = region_device_sz(&g_rdev);
/*
* We need to check the region until we find a 0xff indicating
@@ -56,7 +56,7 @@
// Fill the buffer on first iteration
if (i == 0) {
len = MIN(READ_BUFFER_SIZE, size - offset);
- if (rdev_readat(&rdev, buffer, offset, len) != len)
+ if (rdev_readat(&g_rdev, buffer, offset, len) != len)
return;
}
if (buffer[i] == 0xff) {
@@ -75,29 +75,29 @@
return;
}
- offset = offset;
- rdev_ptr = &rdev;
+ g_offset = offset;
+ g_rdev_ptr = &g_rdev;
}
void flashconsole_tx_byte(unsigned char c)
{
- if (!rdev_ptr)
+ if (!g_rdev_ptr)
return;
- size_t region_size = region_device_sz(rdev_ptr);
+ size_t region_size = region_device_sz(g_rdev_ptr);
- line_buffer[line_offset++] = c;
+ g_line_buffer[g_line_offset++] = c;
- if (line_offset >= LINE_BUFFER_SIZE ||
- offset + line_offset >= region_size || c == '\n') {
+ if (g_line_offset >= LINE_BUFFER_SIZE ||
+ g_offset + g_line_offset >= region_size || c == '\n') {
flashconsole_tx_flush();
}
}
void flashconsole_tx_flush(void)
{
- size_t offset = offset;
- size_t len = line_offset;
+ size_t offset = g_offset;
+ size_t len = g_line_offset;
size_t region_size;
static int busy;
@@ -107,23 +107,23 @@
if (busy)
return;
- if (!rdev_ptr)
+ if (!g_rdev_ptr)
return;
busy = 1;
- region_size = region_device_sz(rdev_ptr);
+ region_size = region_device_sz(g_rdev_ptr);
if (offset + len >= region_size)
len = region_size - offset;
- if (rdev_writeat(&rdev, line_buffer, offset, len) != len)
+ if (rdev_writeat(&g_rdev, g_line_buffer, offset, len) != len)
return;
// If the region is full, stop future write attempts
if (offset + len >= region_size)
return;
- offset = offset + len;
- line_offset = 0;
+ g_offset = offset + len;
+ g_line_offset = 0;
busy = 0;
}
diff --git a/src/mainboard/chuwi/Kconfig b/src/mainboard/chuwi/Kconfig
new file mode 100644
index 0000000..234d863
--- /dev/null
+++ b/src/mainboard/chuwi/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_CHUWI
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/chuwi/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/chuwi/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "CHUWI Innovation And Technology(ShenZhen)co.,Ltd"
+
+endif # VENDOR_CHUWI
diff --git a/src/mainboard/chuwi/Kconfig.name b/src/mainboard/chuwi/Kconfig.name
new file mode 100644
index 0000000..2582c97
--- /dev/null
+++ b/src/mainboard/chuwi/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_CHUWI
+ bool "CHUWI Innovation And Technology(ShenZhen)co.,Ltd"
diff --git a/src/mainboard/chuwi/minibook/Kconfig b/src/mainboard/chuwi/minibook/Kconfig
new file mode 100644
index 0000000..32881b8
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/Kconfig
@@ -0,0 +1,73 @@
+if BOARD_CHUWI_MINIBOOK
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SYSTEM_TYPE_CONVERTIBLE
+ select BOARD_ROMSIZE_KB_8192
+ select SUPERIO_ITE_IT8987E
+ select SOC_INTEL_KABYLAKE
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_INTERNAL_IS_EDP
+ select GENERIC_SPD_BIN
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select ADD_FSP_BINARIES
+ select FSP_USE_REPO
+
+config SPI_FLASH_INCLUDE_ALL_DRIVERS
+ bool
+ default n
+
+config SPI_FLASH
+ bool
+ default y
+
+config SPI_FLASH_WINBOND
+ bool
+ default y
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config VGA_BIOS_ID
+ string
+ default "8086,591c"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MINIBOOK_EC_BIN_PATH
+ string
+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin"
+
+config FSP_FD_PATH
+ string
+ #default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd"
+ default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
+
+config FSP_HEADER_PATH
+ string
+ #default "3rdparty/fsp/AmberLakeFspBinPkg/Include/"
+ default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
+
+config MAX_CPUS
+ int
+ default 4
+
+config CBFS_SIZE
+ hex
+ default 0x600000
+
+config MAINBOARD_DIR
+ string
+ default "chuwi/minibook"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MiniBook"
+
+endif
diff --git a/src/mainboard/chuwi/minibook/Kconfig.name b/src/mainboard/chuwi/minibook/Kconfig.name
new file mode 100644
index 0000000..a8cb30a
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_CHUWI_MINIBOOK
+ bool "MiniBook"
diff --git a/src/mainboard/chuwi/minibook/Makefile.inc b/src/mainboard/chuwi/minibook/Makefile.inc
new file mode 100644
index 0000000..7c7ca2a
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/Makefile.inc
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+#ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+cbfs-files-y += ec.bin
+ec.bin-file := $(call strip_quotes,$(CONFIG_MINIBOOK_EC_BIN_PATH))
+ec.bin-type := raw
+ec.bin-position := 0xffa40000
diff --git a/src/mainboard/chuwi/minibook/acpi/ec.asl b/src/mainboard/chuwi/minibook/acpi/ec.asl
new file mode 100644
index 0000000..ecc384e
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/acpi/ec.asl
@@ -0,0 +1,176 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (EC)
+{
+ Name (_HID, EisaId ("PNP0C09"))
+ Name (_UID, 0)
+
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Name (ACEX, 0)
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ XXX0, 8,
+ XXX1, 8,
+ XXX2, 8,
+ Offset (0x11),
+ KBCD, 8,
+ Offset (0x20),
+ RCMD, 8,
+ RCST, 8,
+ TESR, 8,
+ Offset (0x60),
+ TSR1, 8,
+ TSR2, 8,
+ TSR3, 8,
+ TSI, 4,
+ HYST, 4,
+ TSHT, 8,
+ TSLT, 8,
+ TSSR, 8,
+ CHGR, 16,
+ Offset (0x72),
+ CHGT, 8,
+ Offset (0x7F),
+ LSTE, 1,
+ Offset (0x80),
+ ECWR, 8,
+ XX10, 8,
+ XX11, 16,
+ B1DC, 16,
+ B1FV, 16,
+ B1FC, 16,
+ XX15, 16,
+ B1ST, 8,
+ B1CR, 16,
+ B1RC, 16,
+ B1VT, 16,
+ BPCN, 8,
+ Offset (0xC0),
+ VER1, 8,
+ VER2, 8,
+ RSV1, 8,
+ RSV2, 8,
+ CCI0, 8,
+ CCI1, 8,
+ CCI2, 8,
+ CCI3, 8,
+ CTL0, 8,
+ CTL1, 8,
+ CTL2, 8,
+ CTL3, 8,
+ CTL4, 8,
+ CTL5, 8,
+ CTL6, 8,
+ CTL7, 8,
+ MGI0, 8,
+ MGI1, 8,
+ MGI2, 8,
+ MGI3, 8,
+ MGI4, 8,
+ MGI5, 8,
+ MGI6, 8,
+ MGI7, 8,
+ MGI8, 8,
+ MGI9, 8,
+ MGIA, 8,
+ MGIB, 8,
+ MGIC, 8,
+ MGID, 8,
+ MGIE, 8,
+ MGIF, 8,
+ MGO0, 8,
+ MGO1, 8,
+ MGO2, 8,
+ MGO3, 8,
+ MGO4, 8,
+ MGO5, 8,
+ MGO6, 8,
+ MGO7, 8,
+ MGO8, 8,
+ MGO9, 8,
+ MGOA, 8,
+ MGOB, 8,
+ MGOC, 8,
+ MGOD, 8,
+ MGOE, 8,
+ MGOF, 8,
+ , 3,
+ TPCC, 1,
+ , 2,
+ DRMD, 1,
+ Offset (0xF1)
+ }
+
+ Method (_REG, 2, NotSerialized)
+ {
+ }
+
+ // KEY_RFKILL???
+ Method (_Q01, 0, NotSerialized)
+ {
+ }
+
+ // AC plugged?
+ Method (_Q0A, 0, NotSerialized)
+ {
+ }
+
+ // AC unplugged?
+ Method (_Q0B, 0, NotSerialized)
+ {
+ }
+
+ // Lid open/closed
+ Method (_Q0C, 0, NotSerialized)
+ {
+ }
+
+ // Lid open/closed
+ Method (_Q0D, 0, NotSerialized)
+ {
+ }
+
+ // Brigtness up
+ Method (_Q06, 0, NotSerialized)
+ {
+ }
+
+ // Brigtness down
+ Method (_Q07, 0, NotSerialized)
+ {
+ }
+
+ // Power down event
+ Method (_Q54, 0, NotSerialized)
+ {
+ }
+
+ // ??? USB Type C/UCSI Something?
+ Method (_Q79, 0, NotSerialized)
+ {
+ }
+
+ // ??? DCI (OTG?)
+ Method (_QDD, 0, NotSerialized)
+ {
+ }
+}
diff --git a/src/mainboard/chuwi/minibook/acpi/mainboard.asl b/src/mainboard/chuwi/minibook/acpi/mainboard.asl
new file mode 100644
index 0000000..20d993a
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/acpi/mainboard.asl
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+
+ Method (_LID)
+ {
+ if (LEqual(\_SB.PCI0.LPCB.EC.LSTE,0))
+ {
+ Return (One)
+ }
+ else
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (_STA)
+ {
+ Return (_LID)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+
+ Name (_PRW, Package () { 27, 4 })
+ }
+
+}
diff --git a/src/mainboard/chuwi/minibook/acpi/superio.asl b/src/mainboard/chuwi/minibook/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/acpi/superio.asl
diff --git a/src/mainboard/chuwi/minibook/acpi_tables.c b/src/mainboard/chuwi/minibook/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/acpi_tables.c
diff --git a/src/mainboard/chuwi/minibook/board_info.txt b/src/mainboard/chuwi/minibook/board_info.txt
new file mode 100644
index 0000000..ebb9053
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Chuwi
+Board name: Minibook
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/chuwi/minibook/data.vbt b/src/mainboard/chuwi/minibook/data.vbt
new file mode 100644
index 0000000..16eac95
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/data.vbt
Binary files differ
diff --git a/src/mainboard/chuwi/minibook/devicetree.cb b/src/mainboard/chuwi/minibook/devicetree.cb
new file mode 100644
index 0000000..20ec6d9
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/devicetree.cb
@@ -0,0 +1,264 @@
+chip soc/intel/skylake
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+ register "gen3_dec" = "0x00000069"
+ register "gen4_dec" = "0x0000006d"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "2" # IDK why 2 really
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "PrimaryDisplay" = "Display_iGFX"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "SaGv_Enabled"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 4A | 28A | 24A | 24A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ \
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(5), \
+ .psi3threshold = VR_CFG_AMP(1), \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = VR_CFG_AMP(4), \
+ .voltage_limit = 1520, \
+ .ac_loadline = 1800, \
+ .dc_loadline = 1800, \
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{ \
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(5), \
+ .psi3threshold = VR_CFG_AMP(1), \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = VR_CFG_AMP(28), \
+ .voltage_limit = 1520, \
+ .ac_loadline = 400, \
+ .dc_loadline = 400, \
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{ \
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(5), \
+ .psi3threshold = VR_CFG_AMP(1), \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = VR_CFG_AMP(24), \
+ .voltage_limit = 1520, \
+ .ac_loadline = 570, \
+ .dc_loadline = 570, \
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{ \
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20), \
+ .psi2threshold = VR_CFG_AMP(5), \
+ .psi3threshold = VR_CFG_AMP(1), \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = VR_CFG_AMP(24), \
+ .voltage_limit = 1520, \
+ .ac_loadline = 570, \
+ .dc_loadline = 570, \
+ }"
+
+ # Enable Root Port 6 (WiFi)
+ register "PcieRpEnable[5]" = "1"
+
+ register "PcieRpLtrEnable[5]" = "1"
+
+ # USB
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)
+ register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Wireless
+ register "usb2_ports[8]" = "USB2_PORT_FLEX(OC_SKIP)" # Touchpad
+
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (left)
+
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
+
+ # PL1 override 8W
+ register "tdp_pl1_override" = "8"
+
+ # PL2 override 18W
+ register "tdp_pl2_override" = "18"
+
+ # Send an extra VR mailbox command
+ register "SendVrMbxCmd" = "1"
+
+ # Lock Down
+ register "common_soc_config" = "{ \
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, \
+ }"
+
+ # I2C4 is marked as "IoExpander" in BIOS
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoAcpiHidden, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoPci, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
+ }"
+
+ register "sdcard_cd_gpio_default" = "GPP_B17"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on end # Thermal Subsystem
+ device pci 07.0 on end # ???
+ device pci 08.0 on end # Gaussian Mixture Model
+ device pci 14.0 on end # USB xHCI
+ device pci 14.2 on end # Thermal Subsystem
+ # TODO fill I2C
+ device pci 15.0 on end # I2C Controller #0
+ device pci 15.1 on end # I2C Controller #0
+ device pci 15.2 on end # I2C Controller #0
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 17.0 on end # SATA
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1e.0 on end # Serial IO UART0
+ device pci 1e.3 on end # SPI Controller #0
+ device pci 1e.4 on end # SD Host Controller
+ device pci 1e.6 on end # SD Host Controller
+ device pci 1f.0 on # LPC
+ chip superio/ite/it8987e
+ device pnp 4e.4 off end # System Wake Up Control
+ device pnp 4e.5 on # KBC/Mouse Interface
+ irq 0x70 = 12
+ end
+ device pnp 4e.6 on # KBC/Keyboard Interface
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 4e.a off end # Consumer IR
+ device pnp 4e.f on # Shared Memory/Flash Interface
+ io 0x60 = 0x200
+ irq 0x70 = 0
+ irq 0x71 = 2
+ irq 0xf4 = 9
+ end
+ device pnp 4e.10 on # Real Time Clock
+ io 0x60 = 0x912
+ io 0x62 = 0x910
+ irq 0x70 = 8
+ end
+ device pnp 4e.11 on # Power Management I/F Channel 1 (PMC1)
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ irq 0x70 = 0
+ end
+ device pnp 4e.12 on # Power Management I/F Channel 2 (PMC2)
+ io 0x60 = 0x68
+ io 0x62 = 0x6c
+ irq 0x70 = 0
+ irq 0xf0 = 0
+ end
+ device pnp 4e.13 off end # Serial Peripheral Interface (SSPI)
+ device pnp 4e.14 off end # Platform Environment Control Interface (PECI)
+ device pnp 4e.17 off end # Power Management I/F Channel 3 (PMC3)
+ device pnp 4e.18 off end # Power Management I/F Channel 3 (PMC4)
+ device pnp 4e.19 off end # Power Management I/F Channel 3 (PMC5)
+ end
+ end # LPC Bridge
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ end
+end
diff --git a/src/mainboard/chuwi/minibook/dsdt.asl b/src/mainboard/chuwi/minibook/dsdt.asl
new file mode 100644
index 0000000..ef48745
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/dsdt.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+){
+ //Platform
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/chuwi/minibook/gma-mainboard.ads b/src/mainboard/chuwi/minibook/gma-mainboard.ads
new file mode 100644
index 0000000..452cf26
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/gma-mainboard.ads
@@ -0,0 +1,33 @@
+--
+-- This file is part of the coreboot project.
+--
+-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (Internal,
+ DP1,
+ HDMI1,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/chuwi/minibook/gpio.h b/src/mainboard/chuwi/minibook/gpio.h
new file mode 100644
index 0000000..e8460a7
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/gpio.h
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A0, 0x4000100, 0x1000),
+ /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00),
+ /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00),
+ /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00),
+ /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00),
+ /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0),
+ /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x1000),
+ /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0),
+ /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000),
+ /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x1000),
+ /* SUSWARN#/SUSPWRDNACK */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0),
+ /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0),
+ /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000),
+ /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0),
+ /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x40800102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A19, 0x40000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x42000100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000201, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x44000102, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000102, 0x3000),
+ /* SRCCLKREQ3# */ _PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x3000),
+ /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0),
+ /* SRCCLKREQ5# */ _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0),
+ /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0),
+ /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0),
+ /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000201, 0x800),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x42000100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x46000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000100, 0x1000),
+ /* GSPI1_CS# */ _PAD_CFG_STRUCT(GPP_B19, 0x44000700, 0x0),
+ /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000),
+ /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000),
+ /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000100, 0x1000),
+ /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x2800),
+ /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x2800),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C3, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C4, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C6, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C7, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x44000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x86080102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x4000201, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000102, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000200, 0x2400),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x800),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x82180102, 0x0),
+ /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0),
+ /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0),
+ /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0),
+ /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0),
+ /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0),
+ /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x44000200, 0x2400),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000200, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x44000201, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x4000201, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x44000100, 0x1000),
+ /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000100, 0x1000),
+ /* SATA_DEVSLP1 */ _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E8, 0x44000201, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x3000),
+ /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0),
+ /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0),
+ /* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_E15, 0x44000702, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x3000),
+ /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0),
+ /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0),
+ /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E20, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E21, 0x44000102, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x44000100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000),
+ /* BATLOW# */ _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0),
+ /* ACPRESENT */ _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPD2, 0x4000100, 0x1000),
+ /* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000),
+ /* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0),
+ /* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0),
+ /* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x4000600, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x4000201, 0x0),
+ /* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x4000200, 0x0),
+ /* SLP_S5# */ _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x4000200, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000200, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000200, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000200, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000200, 0x1000),
+ /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000),
+ /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x80180102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x40080100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F10, 0x44000200, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x0),
+ /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0),
+ /* EMMC_DATA0 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0),
+ /* EMMC_DATA1 */ _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0),
+ /* EMMC_DATA2 */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0),
+ /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0),
+ /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0),
+ /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0),
+ /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0),
+ /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0),
+ /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0),
+ /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x44000200, 0x1000),
+ /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000702, 0x0),
+ /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000702, 0x0),
+ /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000702, 0x0),
+ /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000702, 0x0),
+ /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000702, 0x0),
+ /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x3000),
+ /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000702, 0x0),
+ /* SD_WP */ _PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x0),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/chuwi/minibook/hda_verb.c b/src/mainboard/chuwi/minibook/hda_verb.c
new file mode 100644
index 0000000..c654e70
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/hda_verb.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC269VC */
+ 0x10ec0269, /* Vendor ID */
+ 0x10ec0000, /* Subsystem ID */
+ 11, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x10ec0000),
+ AZALIA_PIN_CFG(0, 0x12, 0xb7a60140),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170120),
+ AZALIA_PIN_CFG(0, 0x15, 0x04211010),
+ AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x18, 0x04a11030),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40e4a205),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ /* Intel, KabylakeHDMI */
+ 0x8086280b, /* Vendor ID */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of entries */
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/chuwi/minibook/mainboard.c b/src/mainboard/chuwi/minibook/mainboard.c
new file mode 100644
index 0000000..7f1f114
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/mainboard.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <string.h>
+#include <cbfs.h>
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t ser_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ ser_len = region_device_sz(&cbfs_region);
+ if (ser_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0, ser_len) == ser_len) {
+ serial_number[ser_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
diff --git a/src/mainboard/chuwi/minibook/ramstage.c b/src/mainboard/chuwi/minibook/ramstage.c
new file mode 100644
index 0000000..94f8071
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/chuwi/minibook/romstage.c b/src/mainboard/chuwi/minibook/romstage.c
new file mode 100644
index 0000000..d57adc5
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/romstage.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include "spd/spd.h"
+#include <ec/acpi/ec.h>
+#include <stdint.h>
+#include <stddef.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+
+ printk(BIOS_INFO, "SPD index %d\n", 0);
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ struct region_device spd_rdev;
+
+ mem_cfg->DqPinsInterleaved = 0;
+ if (get_spd_cbfs_rdev(&spd_rdev, 0) < 0)
+ die("spd.bin not found\n");
+ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
+ /* Memory leak is ok since we have memory mapped boot media */
+ // TODO evaluate google/eve way of loading
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
+ //mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+ print_spd_info((uint8_t*)mem_cfg->MemorySpdPtr00);
+
+ mupd->FspmTestConfig.DmiVc1 = 1;
+}
diff --git a/src/mainboard/chuwi/minibook/spd/Makefile.inc b/src/mainboard/chuwi/minibook/spd/Makefile.inc
new file mode 100644
index 0000000..3f2fde0
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/spd/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# It's probably the same SPD used for 16GB version
+SPD_SOURCES += micron # 0b0000 8GB
diff --git a/src/mainboard/chuwi/minibook/spd/micron.spd.hex b/src/mainboard/chuwi/minibook/spd/micron.spd.hex
new file mode 100644
index 0000000..0f1c25f
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/spd/micron.spd.hex
@@ -0,0 +1,32 @@
+91 20 f1 03 05 1a 05 0a 03 11 01 08 0a 00 00 01
+78 78 90 50 90 11 50 e0 90 06 3c 3c 01 90 00 00
+00 b1 00 00 00 00 00 a8 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00 00 00 00 00 00 00 da b0
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/chuwi/minibook/spd/spd.h b/src/mainboard/chuwi/minibook/spd/spd.h
new file mode 100644
index 0000000..36363cc
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/spd/spd.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#include <gpio.h>
+#include "../gpio.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/chuwi/minibook/spd/spd_util.c b/src/mainboard/chuwi/minibook/spd/spd_util.c
new file mode 100644
index 0000000..babd8ef
--- /dev/null
+++ b/src/mainboard/chuwi/minibook/spd/spd_util.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include "spd.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00},
+ {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}};
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ //const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}};
+ const u8 dqs_map[2][8] = {{6, 4, 7, 5, 1, 3, 2, 0},
+ {3, 1, 6, 4, 2, 0, 5, 7}};
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ /* Cannot find these in original BIOS, so use defaults */
+ /* They are valid, probably */
+ const u16 RcompResistor[3] = {200, 81, 162};
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ /* Cannot find these in original BIOS, so use defaults */
+ /* They are valid, probably */
+ static const u16 RcompTarget[5] = {100, 40, 40, 23, 40};
+
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig
new file mode 100644
index 0000000..b8e3258
--- /dev/null
+++ b/src/superio/ite/it8987e/Kconfig
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8987E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc
new file mode 100644
index 0000000..01e4d3e
--- /dev/null
+++ b/src/superio/ite/it8987e/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c
diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h
new file mode 100644
index 0000000..4e265df
--- /dev/null
+++ b/src/superio/ite/it8987e/it8987e.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8987E_H
+#define SUPERIO_ITE_IT8987E_H
+
+#define IT8987E_SWUC 0x04 /* System Wake-Up */
+#define IT8987E_KBCM 0x05 /* PS/2 mouse */
+#define IT8987E_KBCK 0x06 /* PS/2 keyboard */
+#define IT8987E_IR 0x0a /* Consumer IR */
+#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */
+#define IT8987E_RTCT 0x10 /* RTC-like Timer */
+#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */
+#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */
+#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */
+#define IT8987E_PECI 0x14 /* Platform EC Interface */
+#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */
+#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */
+#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */
+
+
+#endif /* SUPERIO_ITE_IT8987E_H */
diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c
new file mode 100644
index 0000000..dce7a6f
--- /dev/null
+++ b/src/superio/ite/it8987e/superio.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+
+#include "it8987e.h"
+
+static void it8987e_init(struct device *dev)
+{
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8987e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, IT8987E_KBCM, PNP_IRQ0, },
+ { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
+ { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, },
+ { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0
+ | PNP_MSC0 | PNP_MSC1 | PNP_MSC2,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe},
+ { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0,
+ 0x07fc, 0x07fc, 0xfff0 },
+ { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 },
+ { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x07ff, 0x07ff },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8987e_ops = {
+ CHIP_NAME("ITE IT8987E Super I/O")
+ .enable_dev = enable_dev,
+};
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