Elyes HAOUAS has uploaded this change for review.

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include/cpu/intel: Remove unneeded includes

Change-Id: Iba1347a2b9ef99f9751b2a4e375ad9503bd53a56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/include/cpu/intel/microcode.h
M src/include/cpu/intel/romstage.h
M src/include/cpu/intel/speedstep.h
3 files changed, 0 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/26769/1

diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 0783ace..f94bee4 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -16,8 +16,6 @@
 #ifndef __CPU__INTEL__MICROCODE__
 #define __CPU__INTEL__MICROCODE__
 
-#include <stdint.h>
-
 void intel_update_microcode_from_cbfs(void);
 /* Find a microcode that matches the revision and platform family returning
  * NULL if none found. */
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 3a9e989..394132d 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -1,8 +1,6 @@
 #ifndef _CPU_INTEL_ROMSTAGE_H
 #define _CPU_INTEL_ROMSTAGE_H
 
-#include <arch/cpu.h>
-
 void mainboard_romstage_entry(unsigned long bist);
 
 /* romstage_main is called from the cache-as-ram assembly file. The return
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 4b556b7..7189c52 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -18,8 +18,6 @@
 #ifndef CPU_INTEL_SPEEDSTEP_H
 #define CPU_INTEL_SPEEDSTEP_H
 
-#include <stdint.h>
-
 /* Magic value used to locate speedstep configuration in the device tree */
 #define SPEEDSTEP_APIC_MAGIC 0xACAC
 

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