Angel Pons has uploaded this change for review.

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sb/intel/i82801ix/Makefile.inc: Sort entries

Sort them by stage execution order, then alphabetically. Place more
complex rules at the end.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ieadda7c264e0288a212b73febbe9f73351cc4de4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/southbridge/intel/i82801ix/Makefile.inc
1 file changed, 16 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42649/1

diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index 5844b91..91ac65b 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -2,31 +2,32 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y)
 
-ramstage-y += i82801ix.c
+bootblock-y += bootblock.c
+bootblock-y += early_init.c
+
+romstage-y += dmi_setup.c
+romstage-y += early_init.c
+romstage-y += early_smbus.c
+
 ramstage-y += fadt.c
-ramstage-y += pci.c
-ramstage-y += lpc.c
-ramstage-y += pcie.c
-ramstage-y += usb_ehci.c
-ramstage-y += sata.c
 ramstage-y += hdaudio.c
-ramstage-y += thermal.c
+ramstage-y += i82801ix.c
+ramstage-y += lpc.c
+ramstage-y += pci.c
+ramstage-y += pcie.c
+ramstage-y += sata.c
 ramstage-y += smbus.c
+ramstage-y += thermal.c
+ramstage-y += usb_ehci.c
 ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
+smm-y += smihandler.c
+
 ifeq ($(CONFIG_SMM_ASEG),y)
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
 endif
-smm-y += smihandler.c
-
-bootblock-y += bootblock.c
-bootblock-y += early_init.c
-
-romstage-y += early_init.c
-romstage-y += early_smbus.c
-romstage-y += dmi_setup.c
 
 endif

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