Patrick Rudolph has uploaded this change for review.

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soc/intel/skylake: Improve comment for DISB

Either documentation or FSP is wrong, as the behaviour of DISB is actually
reversed. Document that and warn about clearing the bit.

Change-Id: I9ca748ddb245cae632e423a417c6a25d52a15354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/soc/intel/skylake/pmc.c
1 file changed, 10 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36650/1

diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index ab9297f..3bc5c68 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -31,7 +31,16 @@
 
 void pmc_set_disb(void)
 {
-	/* Set the DISB after DRAM init */
+	/*
+	 * Set the DISB after DRAM init.
+	 *
+	 * According to Document Number: 332691-002EN
+	 * "Intel 100 Series and Intel C230 Series Chipset Family Platform
+	 * Controller Hub (PCH) Vol2" this bit must be CLEARED after DRAM init.
+	 *
+	 * Tests showed that either documentation or FSP is wrong. Clearing this
+	 * bit here causes full memory training on every boot.
+	 */
 	u32 disb_val;
 #if defined(__SIMPLE_DEVICE__)
 	pci_devfn_t dev = PCH_DEV_PMC;

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