1 comment:
File src/mainboard/google/hatch/variants/baseboard/gpio.c:
/* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
I am wondering if this can be fixed by setting SerialIoSpi1CsEnable: https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h?id=refs/heads/master#n716
Did you try playing with it?
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