Shreesh Chhabbi uploaded patch set #10 to the change originally created by Shreesh Chhabbi.

View Change

src/soc/intel: Enable PCH M.2 RTD3 flow to allow system to enter S0i3.2

BUG=b:160996445
TEST=Build for TGL RVP and Volteer

Change-Id: Ica28d6437a19f3e828b2320965866aba7f883898
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
---
M src/mainboard/google/volteer/dsdt.asl
M src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/intel/tglrvp/dsdt.asl
M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
M src/soc/intel/tigerlake/acpi/pcie.asl
A src/soc/intel/tigerlake/acpi/pmc.asl
6 files changed, 360 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/43600/10

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