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4 comments:

• File src/northbridge/intel/i945/early_init.c:

  • Patch Set #1, Line 555: pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);

    Looks like we could use pci_secondary_reset(int assert), the sequence here repeats a lot. […]

    Done

  • Patch Set #1, Line 666: reg16 |= PCI_BRIDGE_CTL_VGA;

    We can delay setting this to ramstage (with CTL_VGA16)?

    Done

• File src/soc/intel/common/block/pcie/pcie.c:

  • Patch Set #1, Line 40: /* disable parity error response, enable ISA */

    This "enable ISA" is interesting. […]

    Ack

• File src/southbridge/intel/i82801gx/pci.c:

  • Patch Set #1, Line 80: ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */

    Not sure why we set these for a short period of time, init() above disables them again.

    Ack

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