Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35985 )
Change subject: intel/skylake: Implement PCIe RP devicetree update based on DID ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35985/10/src/soc/intel/common/block... File src/soc/intel/common/block/pcie/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/35985/10/src/soc/intel/common/block... PS10, Line 32: <
Shouldn't this be <= ? There are 8 functions possible, right?
Ack
https://review.coreboot.org/c/coreboot/+/35985/10/src/soc/intel/common/block... PS10, Line 79: 24
why 24?
there's a maximum of 24 ports depending on SKU