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1 comment:

• File src/soc/intel/xeon_sp/cpx/acpi.c:

  • Patch Set #3, Line 667:

    // Add DRHD Hardware Unit
    	if (socket == 0 && stack == CSTACK) {
    		printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
    			"Register Base Address: 0x%x\n",
    			DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base);
    		current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL,
    			pcie_seg, reg_base);
    	} else {
    		printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
    			"Register Base Address: 0x%x\n", 0, pcie_seg, reg_base);
    		current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base);
    	}
    

    This is the only place where `reg_base` is used. […]

    Yes. When reg_base is 0x0, this stack is not really a PSTACK (or CSTACK), it needs to be skipped during DMAR generation. In CPX-SP, stack 3 is such stack; the mapping is shown in src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h, search for "IIO Stacks".

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