2 comments:
it's actually slower than simply letting FSP (vs coreboot)
read the SPD data via smbus, so drop it.
Isn't the serial number in SPD cache compared to decide whether memory should be retrained when a DI […]
I'll have to retest swapping SODIMMs here on my Librem CML board and make sure MRC is invalidated/RAM training occurs, but I don't recall it being an issue.
Test: build/boot WYVERN variant, check boot times via cbmem:
w/SPD caching: ~722 ms
w/FSP reading: ~627 ms
Thanks for the numbers Matt. That is helpful. […]
a good chunk is FSP-M:
w/SPD cache:
before ram initialization: 55,526
calling FspMemoryInit: 120,426
returning from FspMemoryInit: 39,648
w/o SPD cache:
before ram initialization: 55,833
calling FspMemoryInit: 6,866
returning from FspMemoryInit: 40,483
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