Amol N Sukerkar uploaded patch set #2 to this change.

View Change

src/security/vboot: Added logic to also verify FSP_S component
and syntax change for verify_stage_if_required.

When VBOOT Stage Verification is enabled, FSP_S component needs
to be verified. This logic has been added.

TEST=Create a coreboot.rom image by enabling CONFIG_VBOOT and
CONFIG_VBOOT_STAGE_VERIFICATION. Verify that the image boots
to authenticated payload and graphics is displayed via HDMI
and Display Port.

Change-Id: I7e2323086ecddc5195d8b55b47cc71f599b5a0b8
Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar@intel.com>
---
M src/security/vboot/Kconfig
M src/security/vboot/Makefile.inc
M src/security/vboot/vboot_logic_ex.c
3 files changed, 57 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32156/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7e2323086ecddc5195d8b55b47cc71f599b5a0b8
Gerrit-Change-Number: 32156
Gerrit-PatchSet: 2
Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar@intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org>
Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar@intel.com>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset