Angel Pons has uploaded this change for review.

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sb/intel/bd82x6x: Deduplicate ME finalization function

Both functions are identical, so we might as well drop one copy.

Change-Id: Ifd24f01dab2b5a6b7d154a8e2b1a69c233a0e727
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me.h
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/me_common.c
4 files changed, 39 insertions(+), 78 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42050/1

diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index d2a3480..7910623 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -111,57 +111,20 @@
 
 #ifdef __SIMPLE_DEVICE__
 
-static void intel_me7_finalize_smm(void)
-{
-	struct me_hfs hfs;
-	u32 reg32;
-	u16 reg16;
-
-	update_mei_base_address();
-
-	/* S3 path will have hidden this device already */
-	if (!is_mei_base_address_valid())
-		return;
-
-	/* Make sure ME is in a mode that expects EOP */
-	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
-	memcpy(&hfs, &reg32, sizeof(u32));
-
-	/* Abort and leave device alone if not normal mode */
-	if (hfs.fpt_bad ||
-	    hfs.working_state != ME_HFS_CWS_NORMAL ||
-	    hfs.operation_mode != ME_HFS_MODE_NORMAL)
-		return;
-
-	/* Try to send EOP command so ME stops accepting other commands */
-	mkhi_end_of_post();
-
-	/* Make sure IO is disabled */
-	reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
-	reg16 &= ~(PCI_COMMAND_MASTER |
-		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-	pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
-
-	/* Hide the PCI device */
-	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
-}
-
 void intel_me_finalize_smm(void)
 {
 	u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
 	switch (did) {
 	case 0x1c3a8086:
-		intel_me7_finalize_smm();
-		break;
 	case 0x1e3a8086:
-		intel_me8_finalize_smm();
+		me_finalize_smm();
 		break;
 	default:
 		printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did);
 	}
 }
 
-#else
+#else /* !__SIMPLE_DEVICE__ */
 
 /* Determine the path that we should take based on ME status */
 static me_bios_path intel_me_path(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index a55a1f2..8fee899 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -245,6 +245,7 @@
 int mkhi_end_of_post(void);
 void update_mei_base_address(void);
 bool is_mei_base_address_valid(void);
+void me_finalize_smm(void);
 int intel_mei_setup(struct device *dev);
 int intel_me_extend_valid(struct device *dev);
 void intel_me_hide(struct device *dev);
@@ -258,7 +259,6 @@
 int intel_early_me_init_done(u8 status);
 
 void intel_me_finalize_smm(void);
-void intel_me8_finalize_smm(void);
 
 typedef struct {
 	u32       major_version  : 16;
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 1a331e9..78f2817 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -99,44 +99,7 @@
 	print_cap("Wireless LAN (WLAN)", cap->wlan);
 }
 
-#ifdef __SIMPLE_DEVICE__
-
-void intel_me8_finalize_smm(void)
-{
-	struct me_hfs hfs;
-	u32 reg32;
-	u16 reg16;
-
-	update_mei_base_address();
-
-	/* S3 path will have hidden this device already */
-	if (!is_mei_base_address_valid())
-		return;
-
-	/* Make sure ME is in a mode that expects EOP */
-	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
-	memcpy(&hfs, &reg32, sizeof(u32));
-
-	/* Abort and leave device alone if not normal mode */
-	if (hfs.fpt_bad ||
-	    hfs.working_state != ME_HFS_CWS_NORMAL ||
-	    hfs.operation_mode != ME_HFS_MODE_NORMAL)
-		return;
-
-	/* Try to send EOP command so ME stops accepting other commands */
-	mkhi_end_of_post();
-
-	/* Make sure IO is disabled */
-	reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
-	reg16 &= ~(PCI_COMMAND_MASTER |
-		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-	pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
-
-	/* Hide the PCI device */
-	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
-}
-
-#else /* !__SIMPLE_DEVICE__ */
+#ifndef __SIMPLE_DEVICE__
 
 /* Determine the path that we should take based on ME status */
 static me_bios_path intel_me_path(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c
index 83e7fe6..9088d44 100644
--- a/src/southbridge/intel/bd82x6x/me_common.c
+++ b/src/southbridge/intel/bd82x6x/me_common.c
@@ -361,6 +361,41 @@
 	return mei_base_address && mei_base_address != (u32 *)0xfffffff0;
 }
 
+void me_finalize_smm(void)
+{
+	struct me_hfs hfs;
+	u32 reg32;
+	u16 reg16;
+
+	update_mei_base_address();
+
+	/* S3 path will have hidden this device already */
+	if (!is_mei_base_address_valid())
+		return;
+
+	/* Make sure ME is in a mode that expects EOP */
+	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+	memcpy(&hfs, &reg32, sizeof(u32));
+
+	/* Abort and leave device alone if not normal mode */
+	if (hfs.fpt_bad ||
+	    hfs.working_state != ME_HFS_CWS_NORMAL ||
+	    hfs.operation_mode != ME_HFS_MODE_NORMAL)
+		return;
+
+	/* Try to send EOP command so ME stops accepting other commands */
+	mkhi_end_of_post();
+
+	/* Make sure IO is disabled */
+	reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
+	reg16 &= ~(PCI_COMMAND_MASTER |
+		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+	pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
+
+	/* Hide the PCI device */
+	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+}
+
 #else
 
 /* Prepare ME for MEI messages */

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