Angel Pons uploaded patch set #3 to this change.

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nb/intel/x4x: Relocate read to TPM base address

Other northbridges do it at the start of raminit. Also, since the TPM
access register is 8 bits wide, use 8-bit ops instead of 32-bit ops.

This register works the same for all TXT-enabled northbridges: If the
TPM access register is valid, and the establishment bit (bit 0) is set,
then a DRTM has not been established on the platform (or the TPM is not
present), and the memory will be unlocked. If bit 0 is clear, then the
memory may remain locked depending on whether it could contain secrets.

Change-Id: Ic36a2810a861758ce733fe80c4e555439e2ffb7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/northbridge/intel/x4x/bootblock.c
M src/northbridge/intel/x4x/raminit.c
2 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45390/3

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