Michael Niewöhner submitted this change.
soc/intel/skylake: Enable SA IMGU depending on devicetree configuration
Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.
All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.
Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
---
M src/mainboard/facebook/monolith/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
12 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index f6c42f1..bede4e3 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -39,7 +39,6 @@
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
- register "SaImguEnable" = "0"
register "Cio2Enable" = "0"
register "PmTimerDisabled" = "1"
register "HeciEnabled" = "0"
@@ -239,6 +238,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # Thermal Subsystem
+ device pci 05.0 off end # SA IMGU
device pci 08.0 on end # Gaussian Mixture Model
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 73f8281..9486147 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -49,7 +49,6 @@
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -247,6 +246,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 on end # SA IMGU
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on
chip drivers/usb/acpi
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 8c638ba..e672940 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -39,7 +39,6 @@
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -267,6 +266,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 on end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 851e240..7ee3116 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -38,7 +38,6 @@
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
- register "SaImguEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -282,6 +281,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 off end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index e4f3112..c454348 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -39,7 +39,6 @@
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -288,6 +287,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 on end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index c7540e9..aef571a 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -44,7 +44,6 @@
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -267,6 +266,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 on end # SA IMGU
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 0c221af..d21f984 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -49,7 +49,6 @@
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
- register "SaImguEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -246,6 +245,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 off end # SA IMGU
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index af50156..64ef501 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -39,7 +39,6 @@
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -268,6 +267,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 on end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index ea3d814..fe5edbe 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -10,7 +10,6 @@
register "DspEnable" = "1"
register "PmTimerDisabled" = "1"
register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
@@ -121,6 +120,7 @@
}"
device domain 0 on
+ device pci 05.0 on end # SA IMGU
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 63861c6..f0759ef 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -45,7 +45,6 @@
register "HeciEnabled" = "1"
register "PmTimerDisabled" = "1"
register "SaGv" = "SaGv_Enabled"
- register "SaImguEnable" = "0"
register "IslVrCmd" = "2"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "4" # 4s
@@ -218,6 +217,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA thermal subsystem
+ device pci 05.0 off end # SA IMGU
device pci 08.0 off end # Gaussian Mixture Model
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on end # USB xHCI
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index cb0d2fc..80e89f6 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -230,7 +230,9 @@
sizeof(params->SerialIoDevMode));
params->PchCio2Enable = config->Cio2Enable;
- params->SaImguEnable = config->SaImguEnable;
+
+ dev = pcidev_path_on_root(SA_DEVFN_IMGU);
+ params->SaImguEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = dev ? dev->enabled : 0;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 404a9f4..33fe52c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -302,7 +302,6 @@
/* Camera */
u8 Cio2Enable;
- u8 SaImguEnable;
/* eMMC and SD */
u8 ScsEmmcHs400Enabled;
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