2 comments:
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
Woops. Just remembered: shl only allows immediate or %cl. Sorry about the suggestion :(.
Sorry, I misread the encoding
/*
* Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with
* total number of LLC ways
*/
movl $IA32_CR_SF_QOS_MASK_2, %ecx
xorl %edx, %edx
wrmsr
Like mentioned on the earlier CL, I think IA32_CR_SF_QOS_MASK_2 is expected to be kept untouched.
Do we have a definition for the reset value for that MSR? I know the doc said to program them it as 0.
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