Anil Kumar K has uploaded this change for review.

View Change

[TEST] mtlrvp: Configure I2C pads by default

Change-Id: Ie52a706f807f4e6345757ff90b0c8a945347b037
---
M src/mainboard/intel/mtlrvp/fw_config.c
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
2 files changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/82095/1

diff --git a/src/mainboard/intel/mtlrvp/fw_config.c b/src/mainboard/intel/mtlrvp/fw_config.c
index eac854c..4b612c4 100644
--- a/src/mainboard/intel/mtlrvp/fw_config.c
+++ b/src/mainboard/intel/mtlrvp/fw_config.c
@@ -76,6 +76,7 @@
 static void fw_config_handle(void *unused)
 {
 	printk(BIOS_INFO, "FW config 0x%" PRIx64 "\n", fw_config_get());
+	return;
 	if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) {
 		printk(BIOS_INFO, "Configure GPIOs for no audio.\n");
 		gpio_configure_pads(audio_disable_pads, ARRAY_SIZE(audio_disable_pads));
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
index 2c48a0e..1f5486c 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
@@ -315,6 +315,21 @@
 	PAD_CFG_GPO(GPP_V22, 1, DEEP),
 	/* Camera: GPP_V23: CRD1_CAM1_RST_N */
 	PAD_CFG_GPO(GPP_V23, 1, DEEP),
+
+	 /* Audio: I2S */
+        PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), /* I2S_MCLK1_OUT */
+        PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), /* I2S0_SCLK_HDR */
+        PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), /* I2S0_SFRM_HDR */
+        PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), /* I2S0_TXD_HDR */
+        PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), /* I2S0_RXD_HDR */
+
+        PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6), /* I2S1_SCLK_HDR */
+        PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6), /* I2S1_SFRM_HDR */
+        PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6), /* I2S1_TXD_HDR */
+        PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6), /* I2S1_RXD_HDR */
+        PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), /* DMIC_CLK_A1 */
+        PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), /* DMIC_DATA1 */
+
 };
 
 /* Early pad configuration in bootblock */
@@ -332,6 +347,21 @@
 	/* SSD */
 	PAD_CFG_GPO(GPP_B15, 0, DEEP), /* M.2_CPU_SSD3_PWREN */
 	PAD_CFG_GPO(GPP_D06, 0, DEEP), /* M.2_CPU_SSD4_PWREN */
+
+	 /* Audio: I2S */
+        PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), /* I2S_MCLK1_OUT */
+        PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), /* I2S0_SCLK_HDR */
+        PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), /* I2S0_SFRM_HDR */
+        PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), /* I2S0_TXD_HDR */
+        PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), /* I2S0_RXD_HDR */
+
+        PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6), /* I2S1_SCLK_HDR */
+        PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6), /* I2S1_SFRM_HDR */
+        PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6), /* I2S1_TXD_HDR */
+        PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6), /* I2S1_RXD_HDR */
+        PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), /* DMIC_CLK_A1 */
+        PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), /* DMIC_DATA1 */
+
 };
 
 static const struct pad_config early_uart_gpio_table[] = {

To view, visit change 82095. To unsubscribe, or for help writing mail filters, visit settings.