View Change

322 comments:

• File src/soc/mediatek/mt8173/dsi.c:

  • Patch Set #1, Line 144: static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid)

    line over 80 characters

  • Patch Set #1, Line 186: static void mtk_dsi_config_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes, const struct edid *edid)

    line over 80 characters

  • Patch Set #1, Line 192: static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, const struct edid *edid)

    line over 80 characters

  • Patch Set #1, Line 354: void *const getmipitx_regbase(u32 dsi_id){

    open brace '{' following function definitions go on the next line

  • Patch Set #1, Line 354: void *const getmipitx_regbase(u32 dsi_id){

    space required before the open brace '{'

  • Patch Set #1, Line 358: void *const getdsi_regbase(u32 dsi_id){

    open brace '{' following function definitions go on the next line

  • Patch Set #1, Line 358: void *const getdsi_regbase(u32 dsi_id){

    space required before the open brace '{'

  • Patch Set #1, Line 360: }

    adding a line without newline at end of file

• File src/soc/mediatek/mt8183/dsi.c:

  • Patch Set #1, Line 1: /*

    trailing whitespace

  • Patch Set #1, Line 2: * This file is part of the coreboot project.

    trailing whitespace

  • Patch Set #1, Line 3: *

    trailing whitespace

  • Patch Set #1, Line 4: * Copyright 2015 MediaTek Inc.

    trailing whitespace

  • Patch Set #1, Line 5: *

    trailing whitespace

  • Patch Set #1, Line 6: * This program is free software; you can redistribute it and/or modify

    trailing whitespace

  • Patch Set #1, Line 7: * it under the terms of the GNU General Public License as published by

    trailing whitespace

  • Patch Set #1, Line 8: * the Free Software Foundation; version 2 of the License.

    trailing whitespace

  • Patch Set #1, Line 9: *

    trailing whitespace

  • Patch Set #1, Line 10: * This program is distributed in the hope that it will be useful,

    trailing whitespace

  • Patch Set #1, Line 11: * but WITHOUT ANY WARRANTY; without even the implied warranty of

    trailing whitespace

  • Patch Set #1, Line 12: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

    trailing whitespace

  • Patch Set #1, Line 13: * GNU General Public License for more details.

    trailing whitespace

  • Patch Set #1, Line 14: */

    DOS line endings

  • Patch Set #1, Line 15:

    DOS line endings

  • Patch Set #1, Line 16: #include <device/mmio.h>

    DOS line endings

  • Patch Set #1, Line 17: #include <console/console.h>

    DOS line endings

  • Patch Set #1, Line 18: #include <delay.h>

    DOS line endings

  • Patch Set #1, Line 19: #include <soc/addressmap.h>

    DOS line endings

  • Patch Set #1, Line 20: #include <soc/dsi.h>

    DOS line endings

  • Patch Set #1, Line 21: #include <timer.h>

    DOS line endings

  • Patch Set #1, Line 22:

    DOS line endings

  • Patch Set #1, Line 23: void *getmipitx_regbase(u32 dsi_id)

    DOS line endings

  • Patch Set #1, Line 24: {

    DOS line endings

  • Patch Set #1, Line 25: return dsi_id ? NULL : (void *)MIPITX_BASE;

    DOS line endings

  • Patch Set #1, Line 26: }

    DOS line endings

  • Patch Set #1, Line 27:

    DOS line endings

  • Patch Set #1, Line 28: void *getdsi_regbase(u32 dsi_id)

    DOS line endings

  • Patch Set #1, Line 29: {

    DOS line endings

  • Patch Set #1, Line 30: return dsi_id ? NULL : (void *)DSI_BASE;

    DOS line endings

  • Patch Set #1, Line 31: }

    DOS line endings

  • Patch Set #1, Line 32:

    DOS line endings

  • Patch Set #1, Line 33: static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid, struct mtk_phy_timing *phy_timing)

    DOS line endings

  • Patch Set #1, Line 33: static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid, struct mtk_phy_timing *phy_timing)

    line over 80 characters

  • Patch Set #1, Line 34: {

    DOS line endings

  • Patch Set #1, Line 35: u32 timcon0, timcon1, timcon2, timcon3;

    DOS line endings

  • Patch Set #1, Line 36: u32 ui, cycle_time, data_rate, bit_per_pixel;

    DOS line endings

  • Patch Set #1, Line 37: struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id);

    DOS line endings

  • Patch Set #1, Line 38:

    DOS line endings

  • Patch Set #1, Line 39: switch (format) {

    DOS line endings

  • Patch Set #1, Line 40: case MIPI_DSI_FMT_RGB565:

    DOS line endings

  • Patch Set #1, Line 41: bit_per_pixel = 16;

    DOS line endings

  • Patch Set #1, Line 42: break;

    DOS line endings

  • Patch Set #1, Line 43: case MIPI_DSI_FMT_RGB666:

    DOS line endings

  • Patch Set #1, Line 44: case MIPI_DSI_FMT_RGB666_PACKED:

    DOS line endings

  • Patch Set #1, Line 45: bit_per_pixel = 18;

    DOS line endings

  • Patch Set #1, Line 46: break;

    DOS line endings

  • Patch Set #1, Line 47: case MIPI_DSI_FMT_RGB888:

    DOS line endings

  • Patch Set #1, Line 48: default:

    DOS line endings

  • Patch Set #1, Line 49: bit_per_pixel = 24;

    DOS line endings

  • Patch Set #1, Line 50: break;

    DOS line endings

  • Patch Set #1, Line 51: }

    DOS line endings

  • Patch Set #1, Line 52:

    DOS line endings

  • Patch Set #1, Line 53: data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes;

    DOS line endings

  • Patch Set #1, Line 54:

    DOS line endings

  • Patch Set #1, Line 55: ui = 1000 / (data_rate / 1000) + 1U;

    DOS line endings

  • Patch Set #1, Line 56: cycle_time = 8000 / (data_rate / 1000) + 1U;

    DOS line endings

  • Patch Set #1, Line 57:

    DOS line endings

  • Patch Set #1, Line 58: phy_timing->lpx = DIV_ROUND_UP(60, cycle_time);

    DOS line endings

  • Patch Set #1, Line 59: phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time);

    DOS line endings

  • Patch Set #1, Line 60: phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time);

    DOS line endings

  • Patch Set #1, Line 61: phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time);

    DOS line endings

  • Patch Set #1, Line 62:

    DOS line endings

  • Patch Set #1, Line 63: phy_timing->ta_go = 4U * phy_timing->lpx;

    DOS line endings

  • Patch Set #1, Line 64: phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;

    DOS line endings

  • Patch Set #1, Line 65: phy_timing->ta_get = 5U * phy_timing->lpx;

    DOS line endings

  • Patch Set #1, Line 66: phy_timing->da_hs_exit = 2U * phy_timing->lpx;

    DOS line endings

  • Patch Set #1, Line 67:

    DOS line endings

  • Patch Set #1, Line 68: phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time);

    DOS line endings

  • Patch Set #1, Line 69: phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU;

    DOS line endings

  • Patch Set #1, Line 70:

    DOS line endings

  • Patch Set #1, Line 71: phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time);

    DOS line endings

  • Patch Set #1, Line 72: phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time);

    DOS line endings

  • Patch Set #1, Line 73: phy_timing->clk_hs_exit = 2U * phy_timing->lpx;

    DOS line endings

  • Patch Set #1, Line 74:

    DOS line endings

  • Patch Set #1, Line 75:

    DOS line endings

  • Patch Set #1, Line 76: timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 |

    DOS line endings

  • Patch Set #1, Line 77: phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24;

    DOS line endings

  • Patch Set #1, Line 78: timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 |

    DOS line endings

  • Patch Set #1, Line 79: phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24;

    DOS line endings

  • Patch Set #1, Line 80: timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 |

    DOS line endings

  • Patch Set #1, Line 81: phy_timing->clk_hs_trail << 24;

    DOS line endings

  • Patch Set #1, Line 82: timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 |

    DOS line endings

  • Patch Set #1, Line 83: phy_timing->clk_hs_exit << 16;

    DOS line endings

  • Patch Set #1, Line 84:

    DOS line endings

  • Patch Set #1, Line 85: dsi_write32(&dsi0->dsi_phy_timecon0, timcon0);

    DOS line endings

  • Patch Set #1, Line 86: dsi_write32(&dsi0->dsi_phy_timecon1, timcon1);

    DOS line endings

  • Patch Set #1, Line 87: dsi_write32(&dsi0->dsi_phy_timecon2, timcon2);

    DOS line endings

  • Patch Set #1, Line 88: dsi_write32(&dsi0->dsi_phy_timecon3, timcon3);

    DOS line endings

  • Patch Set #1, Line 89: }

    DOS line endings

  • Patch Set #1, Line 90:

    DOS line endings

  • Patch Set #1, Line 91: static int mtk_dsi_phy_clk_setting(u32 dsi_id, u32 format, u32 lanes,

    DOS line endings

  • Patch Set #1, Line 92: const struct edid *edid)

    DOS line endings

  • Patch Set #1, Line 93: {

    DOS line endings

  • Patch Set #1, Line 94: unsigned int txdiv, txdiv0, txdiv1;

    DOS line endings

  • Patch Set #1, Line 95: u64 pcw;

    DOS line endings

  • Patch Set #1, Line 96: int data_rate;

    DOS line endings

  • Patch Set #1, Line 97: u32 bpp;

    DOS line endings

  • Patch Set #1, Line 98: void *mipi_tx0 = getmipitx_regbase(dsi_id);

    DOS line endings

  • Patch Set #1, Line 99:

    DOS line endings

  • Patch Set #1, Line 100: if (dsi_id > 0) {

    DOS line endings

  • Patch Set #1, Line 101: printk(BIOS_ERR, "No support dual dsi, please check you panel config\n");

    DOS line endings

  • Patch Set #1, Line 102: return -1;

    DOS line endings

  • Patch Set #1, Line 103: }

    DOS line endings

  • Patch Set #1, Line 104:

    DOS line endings

  • Patch Set #1, Line 105: switch (format) {

    DOS line endings

  • Patch Set #1, Line 106: case MIPI_DSI_FMT_RGB565:

    DOS line endings

  • Patch Set #1, Line 107: bpp = 16;

    DOS line endings

  • Patch Set #1, Line 108: break;

    DOS line endings

  • Patch Set #1, Line 109: case MIPI_DSI_FMT_RGB666:

    DOS line endings

  • Patch Set #1, Line 110: case MIPI_DSI_FMT_RGB666_PACKED:

    DOS line endings

  • Patch Set #1, Line 111: bpp = 18;

    DOS line endings

  • Patch Set #1, Line 112: break;

    DOS line endings

  • Patch Set #1, Line 113: case MIPI_DSI_FMT_RGB888:

    DOS line endings

  • Patch Set #1, Line 114: default:

    DOS line endings

  • Patch Set #1, Line 115: bpp = 24;

    DOS line endings

  • Patch Set #1, Line 116: break;

    DOS line endings

  • Patch Set #1, Line 117: }

    DOS line endings

  • Patch Set #1, Line 118:

    DOS line endings

  • Patch Set #1, Line 119: data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes;

    DOS line endings

  • Patch Set #1, Line 120:

    DOS line endings

  • Patch Set #1, Line 121: printk(BIOS_INFO, "data_rate: %u bps\n", data_rate);

    DOS line endings

  • Patch Set #1, Line 122:

    DOS line endings

  • Patch Set #1, Line 123: if (data_rate >= 2000000000) {

    DOS line endings

  • Patch Set #1, Line 124: txdiv = 1;

    DOS line endings

  • Patch Set #1, Line 125: txdiv0 = 0;

    DOS line endings

  • Patch Set #1, Line 126: txdiv1 = 0;

    DOS line endings

  • Patch Set #1, Line 127: } else if (data_rate >= 1000000000) {

    DOS line endings

  • Patch Set #1, Line 128: txdiv = 2;

    DOS line endings

  • Patch Set #1, Line 129: txdiv0 = 1;

    DOS line endings

  • Patch Set #1, Line 130: txdiv1 = 0;

    DOS line endings

  • Patch Set #1, Line 131: } else if (data_rate >= 500000000) {

    DOS line endings

  • Patch Set #1, Line 132: txdiv = 4;

    DOS line endings

  • Patch Set #1, Line 133: txdiv0 = 2;

    DOS line endings

  • Patch Set #1, Line 134: txdiv1 = 0;

    DOS line endings

  • Patch Set #1, Line 135: } else if (data_rate > 250000000) {

    DOS line endings

  • Patch Set #1, Line 136: txdiv = 8;

    DOS line endings

  • Patch Set #1, Line 137: txdiv0 = 3;

    DOS line endings

  • Patch Set #1, Line 138: txdiv1 = 0;

    DOS line endings

  • Patch Set #1, Line 139: } else if (data_rate >= 125000000) {

    DOS line endings

  • Patch Set #1, Line 140: txdiv = 16;

    DOS line endings

  • Patch Set #1, Line 141: txdiv0 = 4;

    DOS line endings

  • Patch Set #1, Line 142: txdiv1 = 0;

    DOS line endings

  • Patch Set #1, Line 143: } else {

    DOS line endings

  • Patch Set #1, Line 144: printk(BIOS_ERR, "data rate (%u) must be >=50. Please check "

    DOS line endings

  • Patch Set #1, Line 145: "pixel clock (%u), bpp (%u), number of lanes (%u)\n",

    DOS line endings

  • Patch Set #1, Line 146: data_rate, edid->mode.pixel_clock, bpp,

    DOS line endings

  • Patch Set #1, Line 147: lanes);

    DOS line endings

  • Patch Set #1, Line 148: return -1;

    DOS line endings

  • Patch Set #1, Line 149: }

    DOS line endings

  • Patch Set #1, Line 150:

    DOS line endings

  • Patch Set #1, Line 151: dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_CON4, BIT(11) | BIT(10));

    DOS line endings

  • Patch Set #1, Line 152:

    DOS line endings

  • Patch Set #1, Line 153: dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);

    DOS line endings

  • Patch Set #1, Line 154: udelay(30);

    DOS line endings

  • Patch Set #1, Line 155: dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);

    DOS line endings

  • Patch Set #1, Line 156:

    DOS line endings

  • Patch Set #1, Line 157: pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1));

    DOS line endings

  • Patch Set #1, Line 158: pcw <<= 24;

    DOS line endings

  • Patch Set #1, Line 159: pcw /= 26;

    DOS line endings

  • Patch Set #1, Line 160:

    DOS line endings

  • Patch Set #1, Line 161: dsi_write32(mipi_tx0 + MIPITX_PLL_CON0, pcw);

    DOS line endings

  • Patch Set #1, Line 162: dsi_clrsetbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,

    DOS line endings

  • Patch Set #1, Line 163: txdiv0 << 8);

    DOS line endings

  • Patch Set #1, Line 164: udelay(30);

    DOS line endings

  • Patch Set #1, Line 165: dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_EN);

    DOS line endings

  • Patch Set #1, Line 166:

    DOS line endings

  • Patch Set #1, Line 167: /* BG_LPF_EN / BG_CORE_EN */

    DOS line endings

  • Patch Set #1, Line 168: dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF0180);

    DOS line endings

  • Patch Set #1, Line 169: udelay(40);

    DOS line endings

  • Patch Set #1, Line 170: dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF00c0);

    DOS line endings

  • Patch Set #1, Line 171:

    DOS line endings

  • Patch Set #1, Line 172: /* Switch OFF each Lane */

    DOS line endings

  • Patch Set #1, Line 173: dsi_clrbits_le32(mipi_tx0 + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);

    DOS line endings

  • Patch Set #1, Line 174: dsi_clrbits_le32(mipi_tx0 + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);

    DOS line endings

  • Patch Set #1, Line 175: dsi_clrbits_le32(mipi_tx0 + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);

    DOS line endings

  • Patch Set #1, Line 176: dsi_clrbits_le32(mipi_tx0 + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);

    DOS line endings

  • Patch Set #1, Line 177: dsi_clrbits_le32(mipi_tx0 + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);

    DOS line endings

  • Patch Set #1, Line 178:

    DOS line endings

  • Patch Set #1, Line 179: dsi_setbits_le32(mipi_tx0 + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);

    DOS line endings

  • Patch Set #1, Line 180:

    DOS line endings

  • Patch Set #1, Line 181: return data_rate;

    DOS line endings

  • Patch Set #1, Line 182: }

    DOS line endings

  • Patch Set #1, Line 183:

    DOS line endings

  • Patch Set #1, Line 184: static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes,

    DOS line endings

  • Patch Set #1, Line 184: static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes,

    line over 80 characters

  • Patch Set #1, Line 185: const struct edid *edid, struct mtk_phy_timing *phy_timing)

    DOS line endings

  • Patch Set #1, Line 185: const struct edid *edid, struct mtk_phy_timing *phy_timing)

    line over 80 characters

  • Patch Set #1, Line 186: {

    DOS line endings

  • Patch Set #1, Line 187: u32 hsync_active_byte;

    DOS line endings

  • Patch Set #1, Line 188: u32 hbp_byte;

    DOS line endings

  • Patch Set #1, Line 189: u32 hfp_byte, tmp_hfp_byte;

    DOS line endings

  • Patch Set #1, Line 190: u32 vbp_byte;

    DOS line endings

  • Patch Set #1, Line 191: u32 vfp_byte;

    DOS line endings

  • Patch Set #1, Line 192: u32 bpp;

    DOS line endings

  • Patch Set #1, Line 193: u32 packet_fmt;

    DOS line endings

  • Patch Set #1, Line 194: u32 hactive;

    DOS line endings

  • Patch Set #1, Line 195: u32 data_phy_cycles;

    DOS line endings

  • Patch Set #1, Line 196: struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id);

    DOS line endings

  • Patch Set #1, Line 197:

    DOS line endings

  • Patch Set #1, Line 198: if (format == MIPI_DSI_FMT_RGB565)

    DOS line endings

  • Patch Set #1, Line 199: bpp = 2;

    DOS line endings

  • Patch Set #1, Line 200: else

    DOS line endings

  • Patch Set #1, Line 201: bpp = 3;

    DOS line endings

  • Patch Set #1, Line 202:

    DOS line endings

  • Patch Set #1, Line 203: vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -

    DOS line endings

  • Patch Set #1, Line 204: edid->mode.vborder;

    DOS line endings

  • Patch Set #1, Line 205: vfp_byte = edid->mode.vso - edid->mode.vborder;

    DOS line endings

  • Patch Set #1, Line 206:

    DOS line endings

  • Patch Set #1, Line 207: dsi_write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);

    DOS line endings

  • Patch Set #1, Line 208: dsi_write32(&dsi0->dsi_vbp_nl, vbp_byte);

    DOS line endings

  • Patch Set #1, Line 209: dsi_write32(&dsi0->dsi_vfp_nl, vfp_byte);

    DOS line endings

  • Patch Set #1, Line 210: dsi_write32(&dsi0->dsi_vact_nl, edid->mode.va);

    DOS line endings

  • Patch Set #1, Line 211:

    DOS line endings

  • Patch Set #1, Line 212: if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

    DOS line endings

  • Patch Set #1, Line 213: hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -

    DOS line endings

  • Patch Set #1, Line 214: edid->mode.hborder) * bpp - 10;

    DOS line endings

  • Patch Set #1, Line 215: else

    DOS line endings

  • Patch Set #1, Line 216: hbp_byte = (edid->mode.hbl - edid->mode.hso -

    DOS line endings

  • Patch Set #1, Line 217: edid->mode.hborder) * bpp - 10;

    DOS line endings

  • Patch Set #1, Line 218:

    DOS line endings

  • Patch Set #1, Line 219: hsync_active_byte = edid->mode.hspw * bpp - 10;

    DOS line endings

  • Patch Set #1, Line 220:

    DOS line endings

  • Patch Set #1, Line 221: data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +

    DOS line endings

  • Patch Set #1, Line 222: phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2;

    DOS line endings

  • Patch Set #1, Line 223:

    DOS line endings

  • Patch Set #1, Line 224: tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp;

    DOS line endings

  • Patch Set #1, Line 225:

    DOS line endings

  • Patch Set #1, Line 226: if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {

    DOS line endings

  • Patch Set #1, Line 227: if (tmp_hfp_byte > data_phy_cycles * lanes + 18) {

    DOS line endings

  • Patch Set #1, Line 228: hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18;

    DOS line endings

  • Patch Set #1, Line 229: } else {

    DOS line endings

  • Patch Set #1, Line 230: printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");

    DOS line endings

  • Patch Set #1, Line 231: hfp_byte = tmp_hfp_byte;

    DOS line endings

  • Patch Set #1, Line 232: }

    DOS line endings

  • Patch Set #1, Line 233: } else {

    DOS line endings

  • Patch Set #1, Line 234: if (tmp_hfp_byte > data_phy_cycles * lanes + 12) {

    DOS line endings

  • Patch Set #1, Line 235: hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12;

    DOS line endings

  • Patch Set #1, Line 236: } else {

    DOS line endings

  • Patch Set #1, Line 237: printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");

    DOS line endings

  • Patch Set #1, Line 238: hfp_byte = tmp_hfp_byte;

    DOS line endings

  • Patch Set #1, Line 239: }

    DOS line endings

  • Patch Set #1, Line 240: }

    DOS line endings

  • Patch Set #1, Line 241:

    DOS line endings

  • Patch Set #1, Line 242: dsi_write32(&dsi0->dsi_hsa_wc, hsync_active_byte);

    DOS line endings

  • Patch Set #1, Line 243: dsi_write32(&dsi0->dsi_hbp_wc, hbp_byte);

    DOS line endings

  • Patch Set #1, Line 244: dsi_write32(&dsi0->dsi_hfp_wc, hfp_byte);

    DOS line endings

  • Patch Set #1, Line 245:

    DOS line endings

  • Patch Set #1, Line 246: switch (format) {

    DOS line endings

  • Patch Set #1, Line 247: case MIPI_DSI_FMT_RGB888:

    DOS line endings

  • Patch Set #1, Line 248: packet_fmt = PACKED_PS_24BIT_RGB888;

    DOS line endings

  • Patch Set #1, Line 249: break;

    DOS line endings

  • Patch Set #1, Line 250: case MIPI_DSI_FMT_RGB666:

    DOS line endings

  • Patch Set #1, Line 251: packet_fmt = LOOSELY_PS_18BIT_RGB666;

    DOS line endings

  • Patch Set #1, Line 252: break;

    DOS line endings

  • Patch Set #1, Line 253: case MIPI_DSI_FMT_RGB666_PACKED:

    DOS line endings

  • Patch Set #1, Line 254: packet_fmt = PACKED_PS_18BIT_RGB666;

    DOS line endings

  • Patch Set #1, Line 255: break;

    DOS line endings

  • Patch Set #1, Line 256: case MIPI_DSI_FMT_RGB565:

    DOS line endings

  • Patch Set #1, Line 257: packet_fmt = PACKED_PS_16BIT_RGB565;

    DOS line endings

  • Patch Set #1, Line 258: break;

    DOS line endings

  • Patch Set #1, Line 259: default:

    DOS line endings

  • Patch Set #1, Line 260: packet_fmt = PACKED_PS_24BIT_RGB888;

    DOS line endings

  • Patch Set #1, Line 261: break;

    DOS line endings

  • Patch Set #1, Line 262: }

    DOS line endings

  • Patch Set #1, Line 263:

    DOS line endings

  • Patch Set #1, Line 264: hactive = edid->mode.ha;

    DOS line endings

  • Patch Set #1, Line 265: packet_fmt |= (hactive * bpp) & DSI_PS_WC;

    DOS line endings

  • Patch Set #1, Line 266:

    DOS line endings

  • Patch Set #1, Line 267: dsi_write32(&dsi0->dsi_psctrl, 0x2c << 24 | packet_fmt);

    DOS line endings

  • Patch Set #1, Line 268: dsi_write32(&dsi0->dsi_size_con, edid->mode.va << 16 | hactive);

    DOS line endings

  • Patch Set #1, Line 269: dsi_write32(&dsi0->dsi_force_commit, 3);

    DOS line endings

  • Patch Set #1, Line 270: }

    DOS line endings

  • Patch Set #1, Line 271:

    DOS line endings

  • Patch Set #1, Line 272: int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,

    DOS line endings

  • Patch Set #1, Line 273: const struct edid *edid, struct lcm_init_table *init_cmd)

    DOS line endings

  • Patch Set #1, Line 274: {

    DOS line endings

  • Patch Set #1, Line 275: int data_rate;

    DOS line endings

  • Patch Set #1, Line 276: struct dsi_regs *const dsi0 = getdsi_regbase(0);

    DOS line endings

  • Patch Set #1, Line 277: struct mtk_phy_timing *phy_timing = NULL;

    DOS line endings

  • Patch Set #1, Line 278:

    DOS line endings

  • Patch Set #1, Line 279: data_rate = mtk_dsi_phy_clk_setting(0, format, lanes, edid);

    DOS line endings

  • Patch Set #1, Line 280:

    DOS line endings

  • Patch Set #1, Line 281: if (data_rate < 0)

    DOS line endings

  • Patch Set #1, Line 282: return -1;

    DOS line endings

  • Patch Set #1, Line 283:

    DOS line endings

  • Patch Set #1, Line 284: if (dual) {

    DOS line endings

  • Patch Set #1, Line 285: data_rate = mtk_dsi_phy_clk_setting(1, format, lanes, edid);

    DOS line endings

  • Patch Set #1, Line 286: if (data_rate < 0)

    DOS line endings

  • Patch Set #1, Line 287: return -1;

    DOS line endings

  • Patch Set #1, Line 288: }

    DOS line endings

  • Patch Set #1, Line 289:

    DOS line endings

  • Patch Set #1, Line 290: mtk_dsi_reset(0);

    DOS line endings

  • Patch Set #1, Line 291: if (dual)

    DOS line endings

  • Patch Set #1, Line 292: mtk_dsi_reset(1);

    DOS line endings

  • Patch Set #1, Line 293:

    DOS line endings

  • Patch Set #1, Line 294: mtk_dsi_rxtx_control(0, mode_flags, lanes);

    DOS line endings

  • Patch Set #1, Line 295: mtk_dsi_phy_timconfig(0, format, lanes, edid, phy_timing);

    DOS line endings

  • Patch Set #1, Line 296: mtk_dsi_config_vdo_timing(0, mode_flags, format, lanes, edid, phy_timing);

    DOS line endings

  • Patch Set #1, Line 296: mtk_dsi_config_vdo_timing(0, mode_flags, format, lanes, edid, phy_timing);

    line over 80 characters

  • Patch Set #1, Line 297: mtk_dsi_clk_hs_mode_enable(0);

    DOS line endings

  • Patch Set #1, Line 298:

    DOS line endings

  • Patch Set #1, Line 299: push_table(init_cmd);

    DOS line endings

  • Patch Set #1, Line 300:

    DOS line endings

  • Patch Set #1, Line 301: mtk_dsi_set_mode(0, mode_flags);

    DOS line endings

  • Patch Set #1, Line 302: if (dual) {

    DOS line endings

  • Patch Set #1, Line 303: mtk_dsi_set_mode(1, mode_flags);

    DOS line endings

  • Patch Set #1, Line 304: dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN | DSI_DUAL);

    DOS line endings

  • Patch Set #1, Line 305: }

    DOS line endings

  • Patch Set #1, Line 306: mtk_dsi_start(0);

    DOS line endings

  • Patch Set #1, Line 307:

    DOS line endings

  • Patch Set #1, Line 308: return 0;

    DOS line endings

  • Patch Set #1, Line 309: }

    DOS line endings

  • Patch Set #1, Line 310:

    DOS line endings

To view, visit change 34562. To unsubscribe, or for help writing mail filters, visit settings.