Angel Pons has uploaded this change for review.
soc/intel/baytrail/pmutil.c: Constify string arrays
This reduces the differences between Bay Trail and Braswell.
The resulting binary changes, but it shouldn't matter.
Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/soc/intel/baytrail/pmutil.c
1 file changed, 16 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43184/1
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 32e6566..996190e 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -41,8 +41,7 @@
return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8;
}
-static void print_num_status_bits(int num_bits, uint32_t status,
- const char *bit_names[])
+static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[])
{
int i;
@@ -61,7 +60,7 @@
static uint32_t print_smi_status(uint32_t smi_sts)
{
- static const char *smi_sts_bits[] = {
+ static const char *const smi_sts_bits[] = {
[2] = "BIOS",
[4] = "SLP_SMI",
[5] = "APM",
@@ -146,7 +145,7 @@
static uint16_t print_pm1_status(uint16_t pm1_sts)
{
- static const char *pm1_sts_bits[] = {
+ static const char *const pm1_sts_bits[] = {
[0] = "TMROF",
[5] = "GBL",
[8] = "PWRBTN",
@@ -179,7 +178,7 @@
static uint32_t print_tco_status(uint32_t tco_sts)
{
- static const char *tco_sts_bits[] = {
+ static const char *const tco_sts_bits[] = {
[3] = "TIMEOUT",
[17] = "SECOND_TO",
};
@@ -241,7 +240,7 @@
static uint32_t print_gpe_sts(uint32_t gpe_sts)
{
- static const char *gpe_sts_bits[] = {
+ static const char *const gpe_sts_bits[] = {
[1] = "HOTPLUG",
[2] = "SWGPE",
[3] = "PCIE_WAKE0",
@@ -297,17 +296,17 @@
static uint32_t print_alt_sts(uint32_t alt_gpio_smi)
{
uint32_t alt_gpio_sts;
- static const char *alt_gpio_smi_sts_bits[] = {
- [0] = "SUS_GPIO_0",
- [1] = "SUS_GPIO_1",
- [2] = "SUS_GPIO_2",
- [3] = "SUS_GPIO_3",
- [4] = "SUS_GPIO_4",
- [5] = "SUS_GPIO_5",
- [6] = "SUS_GPIO_6",
- [7] = "SUS_GPIO_7",
- [8] = "CORE_GPIO_0",
- [9] = "CORE_GPIO_1",
+ static const char *const alt_gpio_smi_sts_bits[] = {
+ [0] = "SUS_GPIO_0",
+ [1] = "SUS_GPIO_1",
+ [2] = "SUS_GPIO_2",
+ [3] = "SUS_GPIO_3",
+ [4] = "SUS_GPIO_4",
+ [5] = "SUS_GPIO_5",
+ [6] = "SUS_GPIO_6",
+ [7] = "SUS_GPIO_7",
+ [8] = "CORE_GPIO_0",
+ [9] = "CORE_GPIO_1",
[10] = "CORE_GPIO_2",
[11] = "CORE_GPIO_3",
[12] = "CORE_GPIO_4",
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