Arthur Heymans has uploaded this change for review.
soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR
This adds a macro to find an available MTRR(s) to set up CAR.
This added complexity is not required on bootpaths without bootguard
but with bootguard MTRR's have already been set up by the ACM so
we need to figure out at runtime which ones are available.
Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 43 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37190/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 0992d85..d1ae6ca 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -23,6 +23,31 @@
#include <rules.h>
#include <intelblocks/msr.h>
+ /* puts 1 to eax if not found, 0 if found */
+ .macro find_free_mtrr
+ /* Figure put how many MTRRs we have */
+ mov $MTRR_CAP_MSR, %ecx
+ rdmsr
+ movzb %al, %ebx /* Number of variable MTRRs */
+
+ /* Find a free variable MTRR */
+ movl $MTRR_PHYS_MASK(0), %ecx
+1:
+ rdmsr
+ test $MTRR_PHYS_MASK_VALID, %eax
+ jz 2f
+ addl $2, %ecx
+ dec %ebx
+ jnz 1b
+
+ movl $1, %eax
+ jmp 3f
+2:
+ movl $0, %eax
+ decl %ecx
+3:
+ .endm
+
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
@@ -93,15 +118,19 @@
post_code(0x24)
#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
+ find_free_mtrr
+ cmp $1, %eax
+ jne 1f
+ jmp .halt_forever
+1:
/* Configure CAR region as write-back (WB) */
- mov $MTRR_PHYS_BASE(0), %ecx
mov $CONFIG_DCACHE_RAM_BASE, %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
/* Configure the MTRR mask for the size region */
- mov $MTRR_PHYS_MASK(0), %ecx
+ inc %ecx
mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */
dec %eax
not %eax
@@ -109,14 +138,18 @@
movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
wrmsr
#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
+ find_free_mtrr
+ cmp $1, %eax
+ jne 1f
+ jmp .halt_forever
+1:
/* Configure CAR region as write-back (WB) */
- mov $MTRR_PHYS_BASE(0), %ecx
mov $CONFIG_DCACHE_RAM_BASE, %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
- mov $MTRR_PHYS_MASK(0), %ecx
+ incl %ecx
mov $(512 * KiB), %eax /* size mask */
dec %eax
not %eax
@@ -124,13 +157,17 @@
movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
wrmsr
- mov $MTRR_PHYS_BASE(1), %ecx
+ find_free_mtrr
+ cmp $1, %eax
+ jne 1f
+ jmp .halt_forever
+1:
mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
- mov $MTRR_PHYS_MASK(1), %ecx
+ incl %ecx
mov $(256 * KiB), %eax /* size mask */
dec %eax
not %eax
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