Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/21329
to look at the new patch set (#2).
Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path ......................................................................
cpu/intel/car/cache_as_ram.inc: Simplify code path
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE for consistency. This fixes a bug that prevents migrating cpu/intel/slot_1 & nb/intel/i440bx to EARLY_CBMEM_INIT.
Exclude a Hyperthreading-specific code path when building for slot_1 or pga370, which predates HT.
Do not clear MTRRs that will be programmed immediately afterwards.
Remove a block of CAR testing code currently blocked out by #if. Newer CAR code don't even do it anymore.
Do not set %ebp before calling romstage_main(). We know it's not needed.
Clarify the purpose of various code in the file.
Boot tested on ASUS P2B-LS mainboard.
Brought to you by https://review.coreboot.org/c/20977/.
Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Signed-off-by: Keith Hui buurin@gmail.com --- M src/cpu/intel/car/cache_as_ram.inc 1 file changed, 31 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21329/2