Arthur Heymans has uploaded this change for review.
nb/intel/nehalen/raminit.c: Run through clang-format
This improves the readability of the raminit a lot, which was likely
run through a similar tool to wrap around the old 80 char line limit
in the past.
TEST: With BUILD_TIMELESS=1 the hash of the resulting binary is
identical.
Change-Id: I8a4a87884ce15a85f1d8426b981cff4ea4f18a4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/northbridge/intel/nehalem/raminit.c
1 file changed, 1,200 insertions(+), 1,518 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/36084/1
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index dde51f9..98b626d 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -46,61 +46,56 @@
#define NORTHBRIDGE PCI_DEV(0, 0, 0)
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-#define GMA PCI_DEV (0, 0x2, 0x0)
+#define GMA PCI_DEV(0, 0x2, 0x0)
#define HECIDEV PCI_DEV(0, 0x16, 0)
#define HECIBAR 0x10
-#define RANK_IS_POPULATED(info, channel, slot, rank) \
+#define RANK_IS_POPULATED(info, channel, slot, rank) \
((info)->populated_ranks[(channel)][(slot)][(rank)] != 0)
-#define IF_RANK_POPULATED(info, channel, slot, rank) \
+#define IF_RANK_POPULATED(info, channel, slot, rank) \
if (RANK_IS_POPULATED(info, channel, slot, rank))
-#define FOR_EACH_CHANNEL(channel) \
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+#define FOR_EACH_CHANNEL(channel) for (channel = 0; channel < NUM_CHANNELS; channel++)
-#define FOR_EACH_SLOT(slot) \
- for (slot = 0; slot < NUM_SLOTS; slot++)
+#define FOR_EACH_SLOT(slot) for (slot = 0; slot < NUM_SLOTS; slot++)
-#define FOR_ALL_SLOTS(channel, slot) \
- FOR_EACH_CHANNEL(channel) \
- FOR_EACH_SLOT(slot)
+#define FOR_ALL_SLOTS(channel, slot) \
+ FOR_EACH_CHANNEL(channel) \
+ FOR_EACH_SLOT(slot)
-#define FOR_ALL_POPULATED_SLOTS(info, channel, slot) \
- FOR_ALL_SLOTS(channel, slot) \
- IF_RANK_POPULATED(info, channel, slot, 0)
+#define FOR_ALL_POPULATED_SLOTS(info, channel, slot) \
+ FOR_ALL_SLOTS(channel, slot) \
+ IF_RANK_POPULATED(info, channel, slot, 0)
-#define FOR_EACH_RANK(rank) \
- for (rank = 0; rank < NUM_RANKS; rank++)
+#define FOR_EACH_RANK(rank) for (rank = 0; rank < NUM_RANKS; rank++)
-#define FOR_ALL_RANKS(channel, slot, rank) \
- FOR_ALL_SLOTS(channel, slot) \
- FOR_EACH_RANK(rank)
+#define FOR_ALL_RANKS(channel, slot, rank) \
+ FOR_ALL_SLOTS(channel, slot) \
+ FOR_EACH_RANK(rank)
-#define FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \
- FOR_EACH_SLOT(slot) \
- FOR_EACH_RANK(rank)
+#define FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \
+ FOR_EACH_SLOT(slot) \
+ FOR_EACH_RANK(rank)
-#define FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) \
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \
- IF_RANK_POPULATED(info, channel, slot, rank)
+#define FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) \
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \
+ IF_RANK_POPULATED(info, channel, slot, rank)
-#define FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) \
- FOR_ALL_RANKS(channel, slot, rank) \
- IF_RANK_POPULATED(info, channel, slot, rank)
+#define FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) \
+ FOR_ALL_RANKS(channel, slot, rank) \
+ IF_RANK_POPULATED(info, channel, slot, rank)
-#define FOR_EACH_CHANNEL_BACKWARDS(channel) \
+#define FOR_EACH_CHANNEL_BACKWARDS(channel) \
for (channel = NUM_CHANNELS - 1; channel >= 0; channel--)
-#define FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) \
- FOR_EACH_CHANNEL_BACKWARDS(channel) \
- FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank)
+#define FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) \
+ FOR_EACH_CHANNEL_BACKWARDS(channel) \
+ FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank)
-#define FOR_EACH_LANE(lane) \
- for (lane = 0; lane < 8; lane++)
+#define FOR_EACH_LANE(lane) for (lane = 0; lane < 8; lane++)
-#define FOR_EACH_LANE_WITH_ECC(lane) \
- for (lane = 0; lane < 9; lane++)
+#define FOR_EACH_LANE_WITH_ECC(lane) for (lane = 0; lane < 9; lane++)
/* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */
typedef struct {
@@ -123,18 +118,18 @@
u16 timing_offset[2][2][2][9];
u16 timing2_offset[2][2][2][9];
u16 timing2_bounds[2][2][2][9][2];
- u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */
+ u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */
u8 reg2ca9_bit0;
u32 reg_6dc;
u32 reg_6e8;
};
-#include <lib.h> /* Prototypes */
+#include <lib.h> /* Prototypes */
static void clflush(u32 addr)
{
- asm volatile ("clflush (%0)"::"r" (addr));
+ asm volatile("clflush (%0)" ::"r"(addr));
}
typedef struct _u128 {
@@ -142,14 +137,17 @@
u64 hi;
} u128;
-static void read128(u32 addr, u64 * out)
+static void read128(u32 addr, u64 *out)
{
u128 ret;
u128 stor;
- asm volatile ("movdqu %%xmm0, %0\n"
- "movdqa (%2), %%xmm0\n"
- "movdqu %%xmm0, %1\n"
- "movdqu %0, %%xmm0":"+m" (stor), "=m"(ret):"r"(addr));
+ asm volatile(
+ "movdqu %%xmm0, %0\n"
+ "movdqa (%2), %%xmm0\n"
+ "movdqu %%xmm0, %1\n"
+ "movdqu %0, %%xmm0"
+ : "+m"(stor), "=m"(ret)
+ : "r"(addr));
out[0] = ret.lo;
out[1] = ret.hi;
}
@@ -160,8 +158,7 @@
MCHBAR32(0x1d0) = 0;
while (MCHBAR32(0x1d0) & 0x800000)
;
- MCHBAR32(0x1d4) =
- (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits);
+ MCHBAR32(0x1d4) = (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits);
MCHBAR32(0x1d0) = 0x40000000 | addr;
while (MCHBAR32(0x1d0) & 0x800000)
;
@@ -174,8 +171,7 @@
MCHBAR32(0x1d0) = 0;
while (MCHBAR32(0x1d0) & 0x800000)
;
- MCHBAR32(0x1d0) =
- 0x80000000 | (((MCHBAR8(0x246) >> 2) & 3) + 0x361 - addr);
+ MCHBAR32(0x1d0) = 0x80000000 | (((MCHBAR8(0x246) >> 2) & 3) + 0x361 - addr);
while (MCHBAR32(0x1d0) & 0x800000)
;
val = MCHBAR32(0x1d8);
@@ -198,18 +194,18 @@
static void sfence(void)
{
- asm volatile ("sfence");
+ asm volatile("sfence");
}
static inline u16 get_lane_offset(int slot, int rank, int lane)
{
- return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot -
- 0x452 * (lane == 8);
+ return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot
+ - 0x452 * (lane == 8);
}
static inline u16 get_timing_register_addr(int lane, int tm, int slot, int rank)
{
- const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
+ const u16 offs[] = {0x1d, 0xa8, 0xe6, 0x5c};
return get_lane_offset(slot, rank, lane) + offs[(tm + 3) % 4];
}
@@ -219,14 +215,14 @@
return in;
}
-#define gav(x) gav_real (__LINE__, (x))
+#define gav(x) gav_real(__LINE__, (x))
struct raminfo {
- u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */
- u16 fsb_frequency; /* in 1.(1)/2 MHz. */
- u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */
- u8 density[2][2]; /* [CHANNEL][SLOT] */
- u8 populated_ranks[2][2][2]; /* [CHANNEL][SLOT][RANK] */
+ u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */
+ u16 fsb_frequency; /* in 1.(1)/2 MHz. */
+ u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */
+ u8 density[2][2]; /* [CHANNEL][SLOT] */
+ u8 populated_ranks[2][2][2]; /* [CHANNEL][SLOT][RANK] */
int rank_start[2][2][2];
u8 cas_latency;
u8 board_lane_delay[9];
@@ -234,7 +230,7 @@
u8 revision;
u8 max_supported_clock_speed_index;
u8 uma_enabled;
- u8 spd[2][2][151]; /* [CHANNEL][SLOT][BYTE] */
+ u8 spd[2][2][151]; /* [CHANNEL][SLOT][BYTE] */
u8 silicon_revision;
u8 populated_ranks_mask[2];
u8 max_slots_used_in_channel;
@@ -265,13 +261,10 @@
/* Global allocation of timings_car */
timing_bounds_t timings_car[64];
-static void
-write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
- int flag);
+static void write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, int flag);
/* OK */
-static u16
-read_500(struct raminfo *info, int channel, u16 addr, int split)
+static u16 read_500(struct raminfo *info, int channel, u16 addr, int split)
{
u32 val;
info->last_500_command[channel] = 0x80000000;
@@ -279,8 +272,7 @@
while (MCHBAR32(0x500 + (channel << 10)) & 0x800000)
;
MCHBAR32(0x500 + (channel << 10)) =
- 0x80000000 | (((MCHBAR8(0x246 + (channel << 10)) >> 2) & 3)
- + 0xb88 - addr);
+ 0x80000000 | (((MCHBAR8(0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr);
while (MCHBAR32(0x500 + (channel << 10)) & 0x800000)
;
val = MCHBAR32(0x508 + (channel << 10));
@@ -288,9 +280,7 @@
}
/* OK */
-static void
-write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
- int flag)
+static void write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, int flag)
{
if (info->last_500_command[channel] == 0x80000000) {
info->last_500_command[channel] = 0x40000000;
@@ -346,20 +336,16 @@
return ok;
}
-static void
-program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank)
+static void program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank)
{
int lane;
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
write_500(info, channel,
- base +
- info->training.
- lane_timings[2][channel][slot][rank][lane],
+ base + info->training.lane_timings[2][channel][slot][rank][lane],
get_timing_register_addr(lane, 2, slot, rank), 9, 0);
write_500(info, channel,
- base +
- info->training.
- lane_timings[3][channel][slot][rank][lane],
+ base + info->training.lane_timings[3][channel][slot][rank][lane],
get_timing_register_addr(lane, 3, slot, rank), 9, 0);
}
}
@@ -398,47 +384,45 @@
int i, lane;
for (i = 0; i < 2; i++)
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
write_500(info, channel,
- info->training.lane_timings[i +
- 1][channel][slot]
- [rank][lane], get_timing_register_addr(lane,
- i + 1,
- slot,
- rank),
- 9, 0);
+ info->training.lane_timings[i + 1][channel][slot][rank][lane],
+ get_timing_register_addr(lane, i + 1, slot, rank), 9, 0);
}
write_1d0(1, 0x103, 6, 1);
- FOR_EACH_LANE(lane) {
- write_500(info, channel, info->training.lane_timings[0][channel][slot]
- [rank][lane],
+ FOR_EACH_LANE(lane)
+ {
+ write_500(info, channel,
+ info->training.lane_timings[0][channel][slot][rank][lane],
get_timing_register_addr(lane, 0, slot, rank), 9, 0);
}
for (i = 0; i < 2; i++) {
- FOR_EACH_LANE(lane) {
- write_500(info, channel, info->training.lane_timings[i + 1][channel]
- [slot] [rank][lane],
- get_timing_register_addr(lane, i + 1, slot, rank),
- 9, 0);
+ FOR_EACH_LANE(lane)
+ {
+ write_500(info, channel,
+ info->training.lane_timings[i + 1][channel][slot][rank][lane],
+ get_timing_register_addr(lane, i + 1, slot, rank), 9, 0);
}
gav(get_580(channel, ((i + 1) << 2) | (rank << 5)));
}
- gav(read_1d0(0x142, 3)); // = 0x10408118
+ gav(read_1d0(0x142, 3)); // = 0x10408118
MCHBAR8(0x5ff) = 0x0;
MCHBAR8(0x5ff) = 0x80;
write_1d0(0x2, 0x142, 3, 1);
- FOR_EACH_LANE(lane) {
- // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]);
- info->training.lane_timings[2][channel][slot][rank][lane] =
- read_500(info, channel,
- get_timing_register_addr(lane, 2, slot, rank), 9);
- //printk (BIOS_ERR, "after: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]);
+ FOR_EACH_LANE(lane)
+ {
+ // printk (BIOS_ERR, "before: %x\n",
+ // info->training.lane_timings[2][channel][slot][rank][lane]);
+ info->training.lane_timings[2][channel][slot][rank][lane] = read_500(
+ info, channel, get_timing_register_addr(lane, 2, slot, rank), 9);
+ // printk (BIOS_ERR, "after: %x\n",
+ // info->training.lane_timings[2][channel][slot][rank][lane]);
info->training.lane_timings[3][channel][slot][rank][lane] =
- info->training.lane_timings[2][channel][slot][rank][lane] +
- 0x20;
+ info->training.lane_timings[2][channel][slot][rank][lane] + 0x20;
}
}
@@ -446,15 +430,15 @@
{
int slot, rank;
int res = 0;
- FOR_EACH_SLOT(slot) {
+ FOR_EACH_SLOT(slot)
+ {
for (rank = 0; rank < NUM_SLOTS; rank++)
res += info->populated_ranks[channel][slot][rank];
}
return res;
}
-static void
-config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank)
+static void config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank)
{
int add;
@@ -485,21 +469,22 @@
static void set_4cf(struct raminfo *info, int channel, u8 val)
{
- gav(read_500(info, channel, 0x4cf, 4)); // = 0xc2300cf9
+ gav(read_500(info, channel, 0x4cf, 4)); // = 0xc2300cf9
write_500(info, channel, val, 0x4cf, 4, 1);
- gav(read_500(info, channel, 0x659, 4)); // = 0x80300839
+ gav(read_500(info, channel, 0x659, 4)); // = 0x80300839
write_500(info, channel, val, 0x659, 4, 1);
- gav(read_500(info, channel, 0x697, 4)); // = 0x80300839
+ gav(read_500(info, channel, 0x697, 4)); // = 0x80300839
write_500(info, channel, val, 0x697, 4, 1);
}
static void set_334(int zero)
{
int j, k, channel;
- const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b };
+ const u32 val3[] = {0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b};
u32 vd8[2][16];
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
for (j = 0; j < 4; j++) {
u32 a = (j == 1) ? 0x29292929 : 0x31313131;
u32 lmask = (j == 3) ? 0xffff : 0xffffffff;
@@ -512,23 +497,19 @@
c = 0x5f5f;
for (k = 0; k < 2; k++) {
- MCHBAR32(0x138 + 8 * k) =
- (channel << 26) | (j << 24);
+ MCHBAR32(0x138 + 8 * k) = (channel << 26) | (j << 24);
gav(vd8[1][(channel << 3) | (j << 1) | k] =
- MCHBAR32(0x138 + 8 * k));
+ MCHBAR32(0x138 + 8 * k));
gav(vd8[0][(channel << 3) | (j << 1) | k] =
- MCHBAR32(0x13c + 8 * k));
+ MCHBAR32(0x13c + 8 * k));
}
- MCHBAR32(0x334 + (channel << 10) + (j * 0x44)) =
- zero ? 0 : val3[j];
+ MCHBAR32(0x334 + (channel << 10) + (j * 0x44)) = zero ? 0 : val3[j];
MCHBAR32(0x32c + (channel << 10) + (j * 0x44)) =
zero ? 0 : (0x18191819 & lmask);
MCHBAR16(0x34a + (channel << 10) + (j * 0x44)) = c;
- MCHBAR32(0x33c + (channel << 10) + (j * 0x44)) =
- zero ? 0 : (a & lmask);
- MCHBAR32(0x344 + (channel << 10) + (j * 0x44)) =
- zero ? 0 : (a & lmask);
+ MCHBAR32(0x33c + (channel << 10) + (j * 0x44)) = zero ? 0 : (a & lmask);
+ MCHBAR32(0x344 + (channel << 10) + (j * 0x44)) = zero ? 0 : (a & lmask);
}
}
@@ -562,23 +543,21 @@
return -1;
}
-enum {
- DEVICE_TYPE = 2,
- MODULE_TYPE = 3,
- DENSITY = 4,
- RANKS_AND_DQ = 7,
- MEMORY_BUS_WIDTH = 8,
- TIMEBASE_DIVIDEND = 10,
- TIMEBASE_DIVISOR = 11,
- CYCLETIME = 12,
+enum { DEVICE_TYPE = 2,
+ MODULE_TYPE = 3,
+ DENSITY = 4,
+ RANKS_AND_DQ = 7,
+ MEMORY_BUS_WIDTH = 8,
+ TIMEBASE_DIVIDEND = 10,
+ TIMEBASE_DIVISOR = 11,
+ CYCLETIME = 12,
- CAS_LATENCIES_LSB = 14,
- CAS_LATENCIES_MSB = 15,
- CAS_LATENCY_TIME = 16,
- THERMAL_AND_REFRESH = 31,
- REFERENCE_RAW_CARD_USED = 62,
- RANK1_ADDRESS_MAPPING = 63
-};
+ CAS_LATENCIES_LSB = 14,
+ CAS_LATENCIES_MSB = 15,
+ CAS_LATENCY_TIME = 16,
+ THERMAL_AND_REFRESH = 31,
+ REFERENCE_RAW_CARD_USED = 62,
+ RANK1_ADDRESS_MAPPING = 63 };
static void calculate_timings(struct raminfo *info)
{
@@ -593,10 +572,12 @@
/* Find common CAS latency */
supported_cas_latencies = 0x3fe;
- FOR_ALL_POPULATED_SLOTS(info, channel, slot) {
- supported_cas_latencies &= 2 * (info->spd[channel][slot][CAS_LATENCIES_LSB]
- | (info->spd[channel][slot][CAS_LATENCIES_MSB]
- << 8));
+ FOR_ALL_POPULATED_SLOTS(info, channel, slot)
+ {
+ supported_cas_latencies &=
+ 2
+ * (info->spd[channel][slot][CAS_LATENCIES_LSB]
+ | (info->spd[channel][slot][CAS_LATENCIES_MSB] << 8));
}
max_clock_index = min(3, info->max_supported_clock_speed_index);
@@ -604,13 +585,14 @@
cycletime = min_cycletime[max_clock_index];
cas_latency_time = min_cas_latency_time[max_clock_index];
- FOR_ALL_POPULATED_SLOTS(info, channel, slot) {
+ FOR_ALL_POPULATED_SLOTS(info, channel, slot)
+ {
unsigned timebase;
- timebase = 1000 * info->spd[channel][slot][TIMEBASE_DIVIDEND] /
- info->spd[channel][slot][TIMEBASE_DIVISOR];
+ timebase = 1000 * info->spd[channel][slot][TIMEBASE_DIVIDEND]
+ / info->spd[channel][slot][TIMEBASE_DIVISOR];
cycletime = max(cycletime, timebase * info->spd[channel][slot][CYCLETIME]);
- cas_latency_time = max(cas_latency_time, timebase *
- info->spd[channel][slot][CAS_LATENCY_TIME]);
+ cas_latency_time = max(cas_latency_time,
+ timebase * info->spd[channel][slot][CAS_LATENCY_TIME]);
}
if (cycletime > min_cycletime[0])
die("RAM init: Decoded SPD DRAM freq is slower than the controller minimum!");
@@ -630,7 +612,7 @@
if (cas_latency <= min_cas_latency)
break;
supported_cas_latencies &=
- ~(1 << find_highest_bit_set(supported_cas_latencies));
+ ~(1 << find_highest_bit_set(supported_cas_latencies));
}
if (cas_latency != min_cas_latency && clock_speed_index)
@@ -651,137 +633,101 @@
extended_silicon_revision = info->silicon_revision;
if (info->silicon_revision == 0)
- FOR_ALL_SLOTS(channel, slot) {
+ FOR_ALL_SLOTS(channel, slot)
+ {
if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3)
extended_silicon_revision = 4;
}
- FOR_EACH_CHANNEL(channel) {
- FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) {
+ FOR_EACH_CHANNEL(channel)
+ {
+ FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank)
+ {
int card_timing_2;
if (!info->populated_ranks[channel][slot][rank])
continue;
- FOR_EACH_LANE_WITH_ECC(lane) {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
int tm_reg;
int card_timing;
card_timing = 0;
- if ((info->
- spd[channel][slot][MODULE_TYPE] &
- 0xF) == 3) {
+ if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3) {
int reference_card;
- reference_card =
- info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] &
- 0x1f;
+ reference_card = info->spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED]
+ & 0x1f;
if (reference_card == 3)
card_timing =
u16_ffd1188[0][lane]
- [info->
- clock_speed_index];
+ [info->clock_speed_index];
if (reference_card == 5)
card_timing =
u16_ffd1188[1][lane]
- [info->
- clock_speed_index];
+ [info->clock_speed_index];
}
- info->training.
- lane_timings[0][channel][slot][rank]
- [lane] =
- u8_FFFD1218[info->
- clock_speed_index];
- info->training.
- lane_timings[1][channel][slot][rank]
- [lane] = 256;
+ info->training.lane_timings[0][channel][slot][rank][lane] =
+ u8_FFFD1218[info->clock_speed_index];
+ info->training.lane_timings[1][channel][slot][rank][lane] = 256;
for (tm_reg = 2; tm_reg < 4; tm_reg++)
- info->training.
- lane_timings[tm_reg]
- [channel][slot][rank][lane]
- =
- u8_FFFD1240[channel]
- [extended_silicon_revision]
- [lane][2 * slot +
- rank][info->
- clock_speed_index]
+ info->training.lane_timings[tm_reg][channel][slot][rank]
+ [lane] =
+ u8_FFFD1240[channel][extended_silicon_revision]
+ [lane][2 * slot + rank]
+ [info->clock_speed_index]
+ info->max4048[channel]
- +
- u8_FFFD0C78[channel]
- [extended_silicon_revision]
- [info->
- mode4030[channel]][slot]
- [rank][info->
- clock_speed_index]
+ + u8_FFFD0C78[channel]
+ [extended_silicon_revision]
+ [info->mode4030[channel]][slot]
+ [rank][info->clock_speed_index]
+ card_timing;
for (tm_reg = 0; tm_reg < 4; tm_reg++)
write_500(info, channel,
- info->training.
- lane_timings[tm_reg]
- [channel][slot][rank]
- [lane],
- get_timing_register_addr
- (lane, tm_reg, slot,
- rank), 9, 0);
+ info->training.lane_timings[tm_reg][channel]
+ [slot][rank][lane],
+ get_timing_register_addr(lane, tm_reg, slot,
+ rank),
+ 9, 0);
}
card_timing_2 = 0;
if (!(extended_silicon_revision != 4
- || (info->
- populated_ranks_mask[channel] & 5) ==
- 5)) {
- if ((info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] & 0x1F)
+ || (info->populated_ranks_mask[channel] & 5) == 5)) {
+ if ((info->spd[channel][slot][REFERENCE_RAW_CARD_USED] & 0x1F)
== 3)
card_timing_2 =
- u16_FFFE0EB8[0][info->
- clock_speed_index];
- if ((info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] & 0x1F)
+ u16_FFFE0EB8[0][info->clock_speed_index];
+ if ((info->spd[channel][slot][REFERENCE_RAW_CARD_USED] & 0x1F)
== 5)
card_timing_2 =
- u16_FFFE0EB8[1][info->
- clock_speed_index];
+ u16_FFFE0EB8[1][info->clock_speed_index];
}
for (i = 0; i < 3; i++)
write_500(info, channel,
- (card_timing_2 +
- info->max4048[channel]
- +
- u8_FFFD0EF8[channel]
- [extended_silicon_revision]
- [info->
- mode4030[channel]][info->
- clock_speed_index]),
- u16_fffd0c50[i][slot][rank],
- 8, 1);
+ (card_timing_2 + info->max4048[channel]
+ + u8_FFFD0EF8[channel][extended_silicon_revision]
+ [info->mode4030[channel]]
+ [info->clock_speed_index]),
+ u16_fffd0c50[i][slot][rank], 8, 1);
write_500(info, channel,
- (info->max4048[channel] +
- u8_FFFD0C78[channel]
- [extended_silicon_revision][info->
- mode4030
- [channel]]
- [slot][rank][info->
- clock_speed_index]),
+ (info->max4048[channel]
+ + u8_FFFD0C78[channel][extended_silicon_revision]
+ [info->mode4030[channel]][slot][rank]
+ [info->clock_speed_index]),
u16_fffd0c70[slot][rank], 7, 1);
}
if (!info->populated_ranks_mask[channel])
continue;
for (i = 0; i < 3; i++)
write_500(info, channel,
- (info->max4048[channel] +
- info->avg4044[channel]
- +
- u8_FFFD17E0[channel]
- [extended_silicon_revision][info->
- mode4030
- [channel]][info->
- clock_speed_index]),
+ (info->max4048[channel] + info->avg4044[channel]
+ + u8_FFFD17E0[channel][extended_silicon_revision]
+ [info->mode4030[channel]]
+ [info->clock_speed_index]),
u16_fffd0c68[i], 8, 1);
}
}
@@ -843,10 +789,9 @@
some_delay_3_ps_rounded = 0;
extended_silicon_revision = info->silicon_revision;
if (!info->silicon_revision)
- FOR_ALL_SLOTS(channel, slot) {
- if ((info->
- spd[channel][slot][MODULE_TYPE] & 0xF) ==
- 3)
+ FOR_ALL_SLOTS(channel, slot)
+ {
+ if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3)
extended_silicon_revision = 4;
}
if (info->board_lane_delay[7] < 5)
@@ -859,14 +804,13 @@
if (info->revision < 8)
info->revision_flag_1 = 0;
- if (info->revision >= 8 && (info->silicon_revision == 0
- || info->silicon_revision == 1))
+ if (info->revision >= 8 && (info->silicon_revision == 0 || info->silicon_revision == 1))
some_delay_2_ps = 735;
else
some_delay_2_ps = 750;
- if (info->revision >= 0x10 && (info->silicon_revision == 0
- || info->silicon_revision == 1))
+ if (info->revision >= 0x10
+ && (info->silicon_revision == 0 || info->silicon_revision == 1))
some_delay_1_ps = 3929;
else
some_delay_1_ps = 3490;
@@ -880,56 +824,54 @@
info->some_delay_1_cycle_floor = some_delay_1_cycle_floor;
if (info->revision_flag_1)
some_delay_2_ps = halfcycle_ps(info) >> 6;
- some_delay_2_ps +=
- max(some_delay_1_ps - 30,
- 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) +
- 375;
- some_delay_3_ps =
- halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info);
+ some_delay_2_ps += max(some_delay_1_ps - 30,
+ 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000)
+ + 375;
+ some_delay_3_ps = halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info);
if (info->revision_flag_1) {
if (some_delay_3_ps < 150)
some_delay_3_halfcycles = 0;
else
- some_delay_3_halfcycles =
- (some_delay_3_ps << 6) / halfcycle_ps(info);
- some_delay_3_ps_rounded =
- halfcycle_ps(info) * some_delay_3_halfcycles >> 6;
+ some_delay_3_halfcycles = (some_delay_3_ps << 6) / halfcycle_ps(info);
+ some_delay_3_ps_rounded = halfcycle_ps(info) * some_delay_3_halfcycles >> 6;
}
some_delay_2_halfcycles_ceil =
- (some_delay_2_ps + halfcycle_ps(info) - 1) / halfcycle_ps(info) -
- 2 * (some_delay_1_cycle_ceil - 1);
+ (some_delay_2_ps + halfcycle_ps(info) - 1) / halfcycle_ps(info)
+ - 2 * (some_delay_1_cycle_ceil - 1);
if (info->revision_flag_1 && some_delay_3_ps < 150)
some_delay_2_halfcycles_ceil++;
some_delay_2_halfcycles_floor = some_delay_2_halfcycles_ceil;
if (info->revision < 0x10)
- some_delay_2_halfcycles_floor =
- some_delay_2_halfcycles_ceil - 1;
+ some_delay_2_halfcycles_floor = some_delay_2_halfcycles_ceil - 1;
if (!info->revision_flag_1)
some_delay_2_halfcycles_floor++;
info->some_delay_2_halfcycles_ceil = some_delay_2_halfcycles_ceil;
info->some_delay_3_ps_rounded = some_delay_3_ps_rounded;
if ((info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0])
- || (info->populated_ranks[1][0][0]
- && info->populated_ranks[1][1][0]))
+ || (info->populated_ranks[1][0][0] && info->populated_ranks[1][1][0]))
info->max_slots_used_in_channel = 2;
else
info->max_slots_used_in_channel = 1;
for (channel = 0; channel < 2; channel++)
MCHBAR32(0x244 + (channel << 10)) =
- ((info->revision < 8) ? 1 : 0x200) |
- ((2 - info->max_slots_used_in_channel) << 17) |
- (channel << 21) |
- (info->some_delay_1_cycle_floor << 18) | 0x9510;
+ ((info->revision < 8) ? 1 : 0x200)
+ | ((2 - info->max_slots_used_in_channel) << 17) | (channel << 21)
+ | (info->some_delay_1_cycle_floor << 18) | 0x9510;
if (info->max_slots_used_in_channel == 1) {
info->mode4030[0] = (count_ranks_in_channel(info, 0) == 2);
info->mode4030[1] = (count_ranks_in_channel(info, 1) == 2);
} else {
- info->mode4030[0] = ((count_ranks_in_channel(info, 0) == 1) || (count_ranks_in_channel(info, 0) == 2)) ? 2 : 3; /* 2 if 1 or 2 ranks */
+ info->mode4030[0] = ((count_ranks_in_channel(info, 0) == 1)
+ || (count_ranks_in_channel(info, 0) == 2))
+ ? 2
+ : 3; /* 2 if 1 or 2 ranks */
info->mode4030[1] = ((count_ranks_in_channel(info, 1) == 1)
- || (count_ranks_in_channel(info, 1) ==
- 2)) ? 2 : 3;
+ || (count_ranks_in_channel(info, 1) == 2))
+ ? 2
+ : 3;
}
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
int max_of_unk;
int min_of_unk_2;
@@ -947,51 +889,32 @@
for (i = 0; i < 3; i++) {
int unk1;
if (info->revision < 8)
- unk1 =
- u8_FFFD1891[0][channel][info->
- clock_speed_index]
- [i];
- else if (!
- (info->revision >= 0x10
- || info->revision_flag_1))
- unk1 =
- u8_FFFD1891[1][channel][info->
- clock_speed_index]
- [i];
+ unk1 = u8_FFFD1891[0][channel][info->clock_speed_index][i];
+ else if (!(info->revision >= 0x10 || info->revision_flag_1))
+ unk1 = u8_FFFD1891[1][channel][info->clock_speed_index][i];
else
unk1 = 0;
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank)
+ {
int a = 0;
int b = 0;
- if (!info->
- populated_ranks[channel][slot]
- [rank])
+ if (!info->populated_ranks[channel][slot][rank])
continue;
if (extended_silicon_revision == 4
- && (info->
- populated_ranks_mask[channel] &
- 5) != 5) {
- if ((info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] &
- 0x1F) == 3) {
- a = u16_ffd1178[0]
- [info->
- clock_speed_index];
- b = u16_fe0eb8[0][info->
- clock_speed_index];
- } else
- if ((info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED]
- & 0x1F) == 5) {
- a = u16_ffd1178[1]
- [info->
- clock_speed_index];
- b = u16_fe0eb8[1][info->
- clock_speed_index];
- }
+ && (info->populated_ranks_mask[channel] & 5) != 5) {
+ if ((info->spd[channel][slot][REFERENCE_RAW_CARD_USED]
+ & 0x1F)
+ == 3) {
+ a = u16_ffd1178[0][info->clock_speed_index];
+ b = u16_fe0eb8[0][info->clock_speed_index];
+ } else if ((info->spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED]
+ & 0x1F)
+ == 5) {
+ a = u16_ffd1178[1][info->clock_speed_index];
+ b = u16_fe0eb8[1][info->clock_speed_index];
+ }
}
min_of_unk_2 = min(min_of_unk_2, a);
min_of_unk_2 = min(min_of_unk_2, b);
@@ -1001,25 +924,19 @@
}
{
int t;
- t = b +
- u8_FFFD0EF8[channel]
- [extended_silicon_revision]
- [info->
- mode4030[channel]][info->
- clock_speed_index];
+ t = b
+ + u8_FFFD0EF8[channel][extended_silicon_revision]
+ [info->mode4030[channel]]
+ [info->clock_speed_index];
if (unk1 >= t)
- max_of_unk =
- max(max_of_unk,
- unk1 - t);
+ max_of_unk = max(max_of_unk, unk1 - t);
}
}
{
- int t =
- u8_FFFD17E0[channel]
- [extended_silicon_revision][info->
- mode4030
- [channel]]
- [info->clock_speed_index] + min_of_unk_2;
+ int t = u8_FFFD17E0[channel][extended_silicon_revision]
+ [info->mode4030[channel]]
+ [info->clock_speed_index]
+ + min_of_unk_2;
if (unk1 >= t)
max_of_unk = max(max_of_unk, unk1 - t);
}
@@ -1033,22 +950,18 @@
}
}
-static void jedec_read(struct raminfo *info,
- int channel, int slot, int rank,
- int total_rank, u8 addr3, unsigned int value)
+static void jedec_read(struct raminfo *info, int channel, int slot, int rank, int total_rank,
+ u8 addr3, unsigned int value)
{
/* Handle mirrored mapping. */
if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
- addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) |
- ((addr3 >> 1) & 0x10);
+ addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | ((addr3 >> 1) & 0x10);
MCHBAR8(0x271) = addr3 | (MCHBAR8(0x271) & 0xC1);
MCHBAR8(0x671) = addr3 | (MCHBAR8(0x671) & 0xC1);
/* Handle mirrored mapping. */
if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
- value =
- (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8)
- << 1);
+ value = (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8) << 1);
read32p((value << 3) | (total_rank << 28));
@@ -1058,21 +971,18 @@
read32p(total_rank << 28);
}
-enum {
- MR1_RZQ12 = 512,
- MR1_RZQ2 = 64,
- MR1_RZQ4 = 4,
- MR1_ODS34OHM = 2
+enum { MR1_RZQ12 = 512,
+ MR1_RZQ2 = 64,
+ MR1_RZQ4 = 4,
+ MR1_ODS34OHM = 2
};
-enum {
- MR0_BT_INTERLEAVED = 8,
- MR0_DLL_RESET_ON = 256
+enum { MR0_BT_INTERLEAVED = 8,
+ MR0_DLL_RESET_ON = 256
};
-enum {
- MR2_RTT_WR_DISABLED = 0,
- MR2_RZQ2 = 1 << 10
+enum { MR2_RTT_WR_DISABLED = 0,
+ MR2_RZQ2 = 1 << 10
};
static void jedec_init(struct raminfo *info)
@@ -1094,24 +1004,22 @@
} else {
write_recovery = 6;
}
- FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
- auto_self_refresh &=
- (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1;
- self_refresh_temperature &=
- info->spd[channel][slot][THERMAL_AND_REFRESH] & 1;
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank)
+ {
+ auto_self_refresh &= (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1;
+ self_refresh_temperature &= info->spd[channel][slot][THERMAL_AND_REFRESH] & 1;
}
if (auto_self_refresh == 1)
self_refresh_temperature = 0;
dll_on = ((info->silicon_revision != 2 && info->silicon_revision != 3)
- || (info->populated_ranks[0][0][0]
- && info->populated_ranks[0][1][0])
- || (info->populated_ranks[1][0][0]
- && info->populated_ranks[1][1][0]));
+ || (info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0])
+ || (info->populated_ranks[1][0][0] && info->populated_ranks[1][1][0]));
total_rank = 0;
- FOR_EACH_CHANNEL_BACKWARDS(channel) {
+ FOR_EACH_CHANNEL_BACKWARDS(channel)
+ {
int rtt, rtt_wr = MR2_RTT_WR_DISABLED;
int rzq_reg58e;
@@ -1140,28 +1048,20 @@
MCHBAR16(0x58e + (channel << 10)) = rzq_reg58e | 0x82;
MCHBAR16(0x590 + (channel << 10)) = 0x1282;
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank)
+ {
if (info->populated_ranks[channel][slot][rank]) {
- jedec_read(info, channel, slot, rank,
- total_rank, 0x28,
- rtt_wr | (info->
- clock_speed_index
- << 3)
- | (auto_self_refresh << 6) |
- (self_refresh_temperature <<
- 7));
- jedec_read(info, channel, slot, rank,
- total_rank, 0x38, 0);
- jedec_read(info, channel, slot, rank,
- total_rank, 0x18,
+ jedec_read(info, channel, slot, rank, total_rank, 0x28,
+ rtt_wr | (info->clock_speed_index << 3)
+ | (auto_self_refresh << 6)
+ | (self_refresh_temperature << 7));
+ jedec_read(info, channel, slot, rank, total_rank, 0x38, 0);
+ jedec_read(info, channel, slot, rank, total_rank, 0x18,
rtt | MR1_ODS34OHM);
- jedec_read(info, channel, slot, rank,
- total_rank, 6,
- (dll_on << 12) |
- (write_recovery << 9)
- | ((info->cas_latency - 4) <<
- 4) | MR0_BT_INTERLEAVED |
- MR0_DLL_RESET_ON);
+ jedec_read(info, channel, slot, rank, total_rank, 6,
+ (dll_on << 12) | (write_recovery << 9)
+ | ((info->cas_latency - 4) << 4)
+ | MR0_BT_INTERLEAVED | MR0_DLL_RESET_ON);
total_rank++;
}
}
@@ -1171,20 +1071,21 @@
static void program_modules_memory_map(struct raminfo *info, int pre_jedec)
{
unsigned channel, slot, rank;
- unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */
+ unsigned int total_mb[2] = {0, 0}; /* total memory per channel in MB */
unsigned int channel_0_non_interleaved;
- FOR_ALL_RANKS(channel, slot, rank) {
+ FOR_ALL_RANKS(channel, slot, rank)
+ {
if (info->populated_ranks[channel][slot][rank]) {
- total_mb[channel] +=
- pre_jedec ? 256 : (256 << info->
- density[channel][slot] >> info->
- is_x16_module[channel][slot]);
+ total_mb[channel] += pre_jedec
+ ? 256
+ : (256 << info->density[channel][slot]
+ >> info->is_x16_module[channel][slot]);
MCHBAR8(0x208 + rank + 2 * slot + (channel << 10)) =
- (pre_jedec ? (1 | ((1 + 1) << 1)) :
- (info->is_x16_module[channel][slot] |
- ((info->density[channel][slot] + 1) << 1))) |
- 0x80;
+ (pre_jedec ? (1 | ((1 + 1) << 1))
+ : (info->is_x16_module[channel][slot]
+ | ((info->density[channel][slot] + 1) << 1)))
+ | 0x80;
}
MCHBAR16(0x200 + (channel << 10) + 4 * slot + 2 * rank) =
total_mb[channel] >> 6;
@@ -1192,13 +1093,10 @@
info->total_memory_mb = total_mb[0] + total_mb[1];
- info->interleaved_part_mb =
- pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]);
- info->non_interleaved_part_mb =
- total_mb[0] + total_mb[1] - info->interleaved_part_mb;
+ info->interleaved_part_mb = pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]);
+ info->non_interleaved_part_mb = total_mb[0] + total_mb[1] - info->interleaved_part_mb;
channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2;
- MCHBAR32(0x100) = channel_0_non_interleaved |
- (info->non_interleaved_part_mb << 16);
+ MCHBAR32(0x100) = channel_0_non_interleaved | (info->non_interleaved_part_mb << 16);
if (!pre_jedec)
MCHBAR16(0x104) = info->interleaved_part_mb;
}
@@ -1217,81 +1115,67 @@
high_multiplier = 0;
some_delay_ns = 200;
some_delay_3_half_cycles = 4;
- cas_latency_shift = info->silicon_revision == 0
- || info->silicon_revision == 1 ? 1 : 0;
+ cas_latency_shift = info->silicon_revision == 0 || info->silicon_revision == 1 ? 1 : 0;
if (info->revision < 8) {
some_delay_ns = 600;
cas_latency_shift = 0;
}
{
int speed_bit;
- speed_bit =
- ((info->clock_speed_index > 1
- || (info->silicon_revision != 2
- && info->silicon_revision != 3))) ^ (info->revision >=
- 0x10);
- write_500(info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e,
- 3, 1);
- write_500(info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e,
- 3, 1);
+ speed_bit = ((info->clock_speed_index > 1
+ || (info->silicon_revision != 2 && info->silicon_revision != 3)))
+ ^ (info->revision >= 0x10);
+ write_500(info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e, 3, 1);
+ write_500(info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e, 3, 1);
if (info->revision >= 0x10 && info->clock_speed_index <= 1
- && (info->silicon_revision == 2
- || info->silicon_revision == 3))
+ && (info->silicon_revision == 2 || info->silicon_revision == 3))
rmw_1d0(0x116, 5, 2, 4, 1);
}
- MCHBAR32(0x120) = (1 << (info->max_slots_used_in_channel + 28)) |
- 0x188e7f9f;
+ MCHBAR32(0x120) = (1 << (info->max_slots_used_in_channel + 28)) | 0x188e7f9f;
- MCHBAR8(0x124) = info->board_lane_delay[4] +
- ((frequency_01(info) + 999) / 1000);
+ MCHBAR8(0x124) = info->board_lane_delay[4] + ((frequency_01(info) + 999) / 1000);
MCHBAR16(0x125) = 0x1360;
MCHBAR8(0x127) = 0x40;
if (info->fsb_frequency < frequency_11(info) / 2) {
unsigned some_delay_2_half_cycles;
high_multiplier = 1;
- some_delay_2_half_cycles = ps_to_halfcycles(info,
- ((3 *
- fsbcycle_ps(info))
- >> 1) +
- (halfcycle_ps(info)
- *
- reg178_min[info->
- clock_speed_index]
- >> 6)
- +
- 4 *
- halfcycle_ps(info)
- + 2230);
+ some_delay_2_half_cycles = ps_to_halfcycles(
+ info,
+ ((3 * fsbcycle_ps(info))
+ >> 1) + (halfcycle_ps(info) * reg178_min[info->clock_speed_index] >> 6)
+ + 4 * halfcycle_ps(info) + 2230);
some_delay_3_half_cycles =
- min((some_delay_2_half_cycles +
- (frequency_11(info) * 2) * (28 -
- some_delay_2_half_cycles) /
- (frequency_11(info) * 2 -
- 4 * (info->fsb_frequency))) >> 3, 7);
+ min((some_delay_2_half_cycles
+ + (frequency_11(info) * 2) * (28 - some_delay_2_half_cycles)
+ / (frequency_11(info) * 2 - 4 * (info->fsb_frequency)))
+ >> 3,
+ 7);
}
if (MCHBAR8(0x2ca9) & 1)
some_delay_3_half_cycles = 3;
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR32_OR(0x220 + (channel << 10), 0x18001117);
MCHBAR32(0x224 + (channel << 10)) =
- (info->max_slots_used_in_channel - 1) |
- ((info->cas_latency - 5 - info->clock_speed_index)
- << 21) | ((info->max_slots_used_in_channel +
- info->cas_latency - cas_latency_shift - 4) << 16) |
- ((info->cas_latency - cas_latency_shift - 4) << 26) |
- ((info->cas_latency - info->clock_speed_index +
- info->max_slots_used_in_channel - 6) << 8);
- MCHBAR32(0x228 + (channel << 10)) =
- info->max_slots_used_in_channel;
+ (info->max_slots_used_in_channel - 1)
+ | ((info->cas_latency - 5 - info->clock_speed_index) << 21)
+ | ((info->max_slots_used_in_channel + info->cas_latency
+ - cas_latency_shift - 4)
+ << 16)
+ | ((info->cas_latency - cas_latency_shift - 4) << 26)
+ | ((info->cas_latency - info->clock_speed_index
+ + info->max_slots_used_in_channel - 6)
+ << 8);
+ MCHBAR32(0x228 + (channel << 10)) = info->max_slots_used_in_channel;
MCHBAR8(0x239 + (channel << 10)) = 32;
- MCHBAR32(0x248 + (channel << 10)) = (high_multiplier << 24) |
- (some_delay_3_half_cycles << 25) | 0x840000;
+ MCHBAR32(0x248 + (channel << 10)) =
+ (high_multiplier << 24) | (some_delay_3_half_cycles << 25) | 0x840000;
MCHBAR32(0x278 + (channel << 10)) = 0xc362042;
MCHBAR32(0x27c + (channel << 10)) = 0x8b000062;
MCHBAR32(0x24c + (channel << 10)) =
- ((!!info->clock_speed_index) << 17) |
- (((2 + info->clock_speed_index -
- (!!info->clock_speed_index))) << 12) | 0x10200;
+ ((!!info->clock_speed_index) << 17)
+ | (((2 + info->clock_speed_index - (!!info->clock_speed_index))) << 12)
+ | 0x10200;
MCHBAR8(0x267 + (channel << 10)) = 0x4;
MCHBAR16(0x272 + (channel << 10)) = 0x155;
@@ -1328,58 +1212,52 @@
cas_latency_derived = info->cas_latency - info->clock_speed_index + 2;
if (info->clock_speed_index > 1)
cas_latency_derived++;
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR32(0x240 + (channel << 10)) =
- ((info->clock_speed_index == 0) * 0x11000) |
- 0x1002100 | ((2 + info->clock_speed_index) << 4) |
- (info->cas_latency - 3);
- write_500(info, channel, (info->clock_speed_index << 1) | 1,
- 0x609, 6, 1);
- write_500(info, channel,
- info->clock_speed_index + 2 * info->cas_latency - 7,
+ ((info->clock_speed_index == 0) * 0x11000) | 0x1002100
+ | ((2 + info->clock_speed_index) << 4) | (info->cas_latency - 3);
+ write_500(info, channel, (info->clock_speed_index << 1) | 1, 0x609, 6, 1);
+ write_500(info, channel, info->clock_speed_index + 2 * info->cas_latency - 7,
0x601, 6, 1);
MCHBAR32(0x250 + (channel << 10)) =
- ((lane_3_delay + info->clock_speed_index + 9) << 6) |
- (info->board_lane_delay[7] << 2) |
- (info->board_lane_delay[4] << 16) |
- (info->board_lane_delay[1] << 25) |
- (info->board_lane_delay[1] << 29) | 1;
+ ((lane_3_delay + info->clock_speed_index + 9) << 6)
+ | (info->board_lane_delay[7] << 2) | (info->board_lane_delay[4] << 16)
+ | (info->board_lane_delay[1] << 25) | (info->board_lane_delay[1] << 29)
+ | 1;
MCHBAR32(0x254 + (channel << 10)) =
- (info->board_lane_delay[1] >> 3) |
- ((info->board_lane_delay[8] + 4 * info->use_ecc) << 6) |
- 0x80 | (info->board_lane_delay[6] << 1) |
- (info->board_lane_delay[2] << 28) |
- (cas_latency_derived << 16) | 0x4700000;
+ (info->board_lane_delay[1] >> 3)
+ | ((info->board_lane_delay[8] + 4 * info->use_ecc) << 6) | 0x80
+ | (info->board_lane_delay[6] << 1) | (info->board_lane_delay[2] << 28)
+ | (cas_latency_derived << 16) | 0x4700000;
MCHBAR32(0x258 + (channel << 10)) =
- ((info->board_lane_delay[5] + info->clock_speed_index +
- 9) << 12) | ((info->clock_speed_index -
- info->cas_latency + 12) << 8) |
- (info->board_lane_delay[2] << 17) |
- (info->board_lane_delay[4] << 24) | 0x47;
- MCHBAR32(0x25c + (channel << 10)) =
- (info->board_lane_delay[1] << 1) |
- (info->board_lane_delay[0] << 8) | 0x1da50000;
+ ((info->board_lane_delay[5] + info->clock_speed_index + 9) << 12)
+ | ((info->clock_speed_index - info->cas_latency + 12) << 8)
+ | (info->board_lane_delay[2] << 17) | (info->board_lane_delay[4] << 24)
+ | 0x47;
+ MCHBAR32(0x25c + (channel << 10)) = (info->board_lane_delay[1] << 1)
+ | (info->board_lane_delay[0] << 8)
+ | 0x1da50000;
MCHBAR8(0x264 + (channel << 10)) = 0xff;
- MCHBAR8(0x5f8 + (channel << 10)) =
- (cas_latency_shift << 3) | info->use_ecc;
+ MCHBAR8(0x5f8 + (channel << 10)) = (cas_latency_shift << 3) | info->use_ecc;
}
program_modules_memory_map(info, 1);
MCHBAR16(0x610) = (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9)
- | (MCHBAR16(0x610) & 0x1C3) | 0x3C;
+ | (MCHBAR16(0x610) & 0x1C3) | 0x3C;
MCHBAR16_OR(0x612, 0x100);
MCHBAR16_OR(0x214, 0x3E00);
for (i = 0; i < 8; i++) {
- pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i,
- (info->total_memory_mb - 64) | !i | 2);
- pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0);
+ pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x80 + 4 * i,
+ (info->total_memory_mb - 64) | !i | 2);
+ pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0);
}
}
#define DEFAULT_PCI_MMIO_SIZE 2048
-#define HOST_BRIDGE PCI_DEVFN(0, 0)
+#define HOST_BRIDGE PCI_DEVFN(0, 0)
static unsigned int get_mmio_size(void)
{
@@ -1419,13 +1297,11 @@
if (info->uma_enabled) {
u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC);
gav(t);
- const int uma_sizes_gtt[16] =
- { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
+ const int uma_sizes_gtt[16] = {0, 1, 0, 2, 0, 0, 0, 0,
+ 0, 2, 3, 4, 42, 42, 42, 42};
/* Igd memory */
- const int uma_sizes_igd[16] = {
- 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352,
- 256, 512
- };
+ const int uma_sizes_igd[16] = {0, 0, 0, 0, 0, 32, 48, 64,
+ 128, 256, 96, 160, 224, 352, 256, 512};
uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];
uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
@@ -1437,8 +1313,8 @@
if (TOM == 4096)
TOM = 4032;
TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64);
- TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64)
- , TOUUD), 64);
+ TOLUD = ALIGN_DOWN(
+ min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64), TOUUD), 64);
memory_remap = 0;
if (TOUUD - TOLUD > 64) {
memory_remap = 1;
@@ -1490,8 +1366,7 @@
for (i = 0; i < ARRAY_SIZE(memory_map); i++) {
current_limit = max(current_limit, memory_map[i] & ~1);
pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80,
- (memory_map[i] & 1) | ALIGN_DOWN(current_limit -
- 1, 64) | 2);
+ (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2);
pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0);
}
}
@@ -1507,8 +1382,7 @@
;
if (!info->heci_bar)
- gav(info->heci_bar =
- pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8);
+ gav(info->heci_bar = pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8);
if (!info->memory_reserved_for_heci_mb) {
/* Wait for ME to be ready */
intel_early_me_init();
@@ -1516,26 +1390,25 @@
}
for (i = 0; i < 3; i++)
- gav(capid0[i] =
- pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2)));
+ gav(capid0[i] = pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2)));
gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID));
info->max_supported_clock_speed_index = (~capid0[1] & 7);
if ((capid0[1] >> 11) & 1)
info->uma_enabled = 0;
else
- gav(info->uma_enabled =
- pci_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8);
- /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */
+ gav(info->uma_enabled = pci_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8);
+ /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 =>
+ * 00020655.00010800.029ae3ff.bfebfbff */
info->silicon_revision = 0;
if (capid0[2] & 2) {
info->silicon_revision = 0;
info->max_supported_clock_speed_index = 2;
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
if (info->populated_ranks[channel][0][0]
- && (info->spd[channel][0][MODULE_TYPE] & 0xf) ==
- 3) {
+ && (info->spd[channel][0][MODULE_TYPE] & 0xf) == 3) {
info->silicon_revision = 2;
info->max_supported_clock_speed_index = 1;
}
@@ -1571,17 +1444,14 @@
return;
for (tm = 0; tm < 4; tm++)
- FOR_ALL_RANKS(channel, slot, rank) {
- FOR_EACH_LANE_WITH_ECC(lane) {
+ FOR_ALL_RANKS(channel, slot, rank)
+ {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
write_500(info, channel,
- info->
- cached_training->
- lane_timings[tm]
- [channel][slot][rank]
- [lane],
- get_timing_register_addr
- (lane, tm, slot,
- rank), 9, 0);
+ info->cached_training
+ ->lane_timings[tm][channel][slot][rank][lane],
+ get_timing_register_addr(lane, tm, slot, rank), 9, 0);
}
}
write_1d0(info->cached_training->reg_178, 0x178, 7, 1);
@@ -1592,28 +1462,25 @@
{
int channel, slot, rank, lane, i;
printk(RAM_DEBUG, "Timings:\n");
- FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
- printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel,
- slot, rank);
- FOR_EACH_LANE_WITH_ECC(lane) {
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank)
+ {
+ printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank);
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
printk(RAM_DEBUG, "lane %d: ", lane);
for (i = 0; i < 4; i++) {
printk(RAM_DEBUG, "%x (%x) ",
read_500(info, channel,
- get_timing_register_addr
- (lane, i, slot, rank),
+ get_timing_register_addr(lane, i, slot, rank),
9),
- info->training.
- lane_timings[i][channel][slot][rank]
- [lane]);
+ info->training
+ .lane_timings[i][channel][slot][rank][lane]);
}
printk(RAM_DEBUG, "\n");
}
}
- printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7),
- info->training.reg_178);
- printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),
- info->training.reg_10b);
+ printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), info->training.reg_178);
+ printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b);
}
/* Read timings and other registers that need to be restored verbatim and
@@ -1625,25 +1492,26 @@
int channel, slot, rank, lane, i;
train = info->training;
- FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
- FOR_EACH_LANE_WITH_ECC(lane) {
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank)
+ {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
for (i = 0; i < 4; i++)
- train.lane_timings[i][channel][slot][rank][lane] =
- read_500(info, channel,
- get_timing_register_addr(lane, i, slot,
- rank), 9);
+ train.lane_timings[i][channel][slot][rank][lane] = read_500(
+ info, channel,
+ get_timing_register_addr(lane, i, slot, rank), 9);
}
}
train.reg_178 = read_1d0(0x178, 7);
train.reg_10b = read_1d0(0x10b, 6);
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
u32 reg32;
reg32 = MCHBAR32((channel << 10) + 0x274);
train.reg274265[channel][0] = reg32 >> 16;
train.reg274265[channel][1] = reg32 & 0xffff;
- train.reg274265[channel][2] =
- MCHBAR16((channel << 10) + 0x265) >> 8;
+ train.reg274265[channel][2] = MCHBAR16((channel << 10) + 0x265) >> 8;
}
train.reg2ca9_bit0 = MCHBAR8(0x2ca9) & 1;
train.reg_6dc = MCHBAR32(0x6dc);
@@ -1653,15 +1521,13 @@
printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8);
/* Save the MRC S3 restore data to cbmem */
- mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
- &train, sizeof(train));
+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &train, sizeof(train));
}
static const struct ram_training *get_cached_training(void)
{
struct region_device rdev;
- if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
- &rdev))
+ if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev))
return 0;
return (void *)rdev_mmap_full(&rdev);
}
@@ -1669,10 +1535,9 @@
/* FIXME: add timeout. */
static void wait_heci_ready(void)
{
- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c
+ while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c
;
- write32((DEFAULT_HECIBAR + 0x4),
- (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
+ write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
}
/* FIXME: add timeout. */
@@ -1688,10 +1553,8 @@
do
csr.raw = read32(DEFAULT_HECIBAR + 0x4);
- while (len >
- csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
- csr.csr.buffer_read_ptr))
- ;
+ while (len
+ > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr));
}
static void send_heci_packet(struct mei_header *head, u32 *payload)
@@ -1702,7 +1565,7 @@
wait_heci_cb_avail(len + 1);
/* FIXME: handle leftovers correctly. */
- write32(DEFAULT_HECIBAR + 0, *(u32 *) head);
+ write32(DEFAULT_HECIBAR + 0, *(u32 *)head);
for (i = 0; i < len - 1; i++)
write32(DEFAULT_HECIBAR + 0, payload[i]);
@@ -1710,8 +1573,7 @@
write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4);
}
-static void
-send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress)
+static void send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress)
{
struct mei_header head;
int maxlen;
@@ -1730,16 +1592,15 @@
head.reserved = 0;
head.client_address = clientaddress;
head.host_address = hostaddress;
- send_heci_packet(&head, (u32 *) msg);
+ send_heci_packet(&head, (u32 *)msg);
len -= cur;
msg += cur;
}
}
/* FIXME: Add timeout. */
-static int
-recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet,
- u32 *packet_size)
+static int recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet,
+ u32 *packet_size)
{
union {
struct mei_csr csr;
@@ -1750,29 +1611,24 @@
write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
do {
csr.raw = read32(DEFAULT_HECIBAR + 0xc);
- }
- while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr)
- ;
- *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);
+ } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
+ *(u32 *)head = read32(DEFAULT_HECIBAR + 0x8);
if (!head->length) {
- write32(DEFAULT_HECIBAR + 0x4,
- read32(DEFAULT_HECIBAR + 0x4) | 2);
+ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
*packet_size = 0;
return 0;
}
- if (head->length + 4 > 4 * csr.csr.buffer_depth
- || head->length > *packet_size) {
+ if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) {
*packet_size = 0;
return -1;
}
do
csr.raw = read32(DEFAULT_HECIBAR + 0xc);
- while (((head->length + 3) >> 2) >
- (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr))
- ;
+ while (((head->length + 3) >> 2)
+ > (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr));
- for (i = 0; i < (head->length + 3) >> 2; i++)
+ for (i = 0; i<(head->length + 3)>> 2; i++)
packet[i++] = read32(DEFAULT_HECIBAR + 0x8);
*packet_size = head->length;
if (!csr.csr.ready)
@@ -1782,8 +1638,7 @@
}
/* FIXME: Add timeout. */
-static int
-recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size)
+static int recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size)
{
struct mei_header head;
int current_position;
@@ -1792,9 +1647,9 @@
while (1) {
u32 current_size;
current_size = *message_size - current_position;
- if (recv_heci_packet
- (info, &head, message + (current_position >> 2),
- ¤t_size) == -1)
+ if (recv_heci_packet(info, &head, message + (current_position >> 2),
+ ¤t_size)
+ == -1)
break;
if (!current_size)
break;
@@ -1830,16 +1685,20 @@
u64 heci_uma_addr;
u32 memory_reserved_for_heci_mb;
u16 c3;
- } __packed msg = {
- 0, MKHI_SET_UMA, 0, 0,
- 0x82,
- info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0};
+ } __packed msg = {0,
+ MKHI_SET_UMA,
+ 0,
+ 0,
+ 0x82,
+ info->heci_uma_addr,
+ info->memory_reserved_for_heci_mb,
+ 0};
u32 reply_size;
- send_heci_message((u8 *) & msg, sizeof(msg), 0, 7);
+ send_heci_message((u8 *)&msg, sizeof(msg), 0, 7);
reply_size = sizeof(reply);
- if (recv_heci_message(info, (u32 *) & reply, &reply_size) == -1)
+ if (recv_heci_message(info, (u32 *)&reply, &reply_size) == -1)
return;
if (reply.command != (MKHI_SET_UMA | (1 << 7)))
@@ -1850,7 +1709,7 @@
{
u32 reg44;
- reg44 = pci_read_config32(HECIDEV, 0x44); // = 0x80010020
+ reg44 = pci_read_config32(HECIDEV, 0x44); // = 0x80010020
info->memory_reserved_for_heci_mb = 0;
info->heci_uma_addr = 0;
if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20)))
@@ -1858,34 +1717,24 @@
info->heci_bar = pci_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0;
info->memory_reserved_for_heci_mb = reg44 & 0x3f;
- info->heci_uma_addr =
- ((u64)
- ((((u64) pci_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) -
- info->memory_reserved_for_heci_mb)) << 20;
+ info->heci_uma_addr = ((u64)((((u64)pci_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6)
+ - info->memory_reserved_for_heci_mb))
+ << 20;
pci_read_config32(NORTHBRIDGE, DMIBAR);
if (info->memory_reserved_for_heci_mb) {
- write32(DEFAULT_DMIBAR + 0x14,
- read32(DEFAULT_DMIBAR + 0x14) & ~0x80);
- write32(DEFAULT_RCBA + 0x14,
- read32(DEFAULT_RCBA + 0x14) & ~0x80);
- write32(DEFAULT_DMIBAR + 0x20,
- read32(DEFAULT_DMIBAR + 0x20) & ~0x80);
- write32(DEFAULT_RCBA + 0x20,
- read32(DEFAULT_RCBA + 0x20) & ~0x80);
- write32(DEFAULT_DMIBAR + 0x2c,
- read32(DEFAULT_DMIBAR + 0x2c) & ~0x80);
- write32(DEFAULT_RCBA + 0x30,
- read32(DEFAULT_RCBA + 0x30) & ~0x80);
- write32(DEFAULT_DMIBAR + 0x38,
- read32(DEFAULT_DMIBAR + 0x38) & ~0x80);
- write32(DEFAULT_RCBA + 0x40,
- read32(DEFAULT_RCBA + 0x40) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x14, read32(DEFAULT_DMIBAR + 0x14) & ~0x80);
+ write32(DEFAULT_RCBA + 0x14, read32(DEFAULT_RCBA + 0x14) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x20, read32(DEFAULT_DMIBAR + 0x20) & ~0x80);
+ write32(DEFAULT_RCBA + 0x20, read32(DEFAULT_RCBA + 0x20) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x2c, read32(DEFAULT_DMIBAR + 0x2c) & ~0x80);
+ write32(DEFAULT_RCBA + 0x30, read32(DEFAULT_RCBA + 0x30) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x38, read32(DEFAULT_DMIBAR + 0x38) & ~0x80);
+ write32(DEFAULT_RCBA + 0x40, read32(DEFAULT_RCBA + 0x40) & ~0x80);
- write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK
- write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK
- while ((read16(DEFAULT_RCBA + 0x46) & 2) &&
- read16(DEFAULT_DMIBAR + 0x3e) & 2)
+ write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK
+ write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK
+ while ((read16(DEFAULT_RCBA + 0x46) & 2) && read16(DEFAULT_DMIBAR + 0x3e) & 2)
;
}
@@ -1895,16 +1744,14 @@
pci_write_config32(HECIDEV, 0x10, 0x0);
pci_write_config8(HECIDEV, 0x4, 0x0);
-
}
static int have_match_ranks(struct raminfo *info, int channel, int ranks)
{
int ranks_in_channel;
- ranks_in_channel = info->populated_ranks[channel][0][0]
- + info->populated_ranks[channel][0][1]
- + info->populated_ranks[channel][1][0]
- + info->populated_ranks[channel][1][1];
+ ranks_in_channel =
+ info->populated_ranks[channel][0][0] + info->populated_ranks[channel][0][1]
+ + info->populated_ranks[channel][1][0] + info->populated_ranks[channel][1][1];
/* empty channel */
if (ranks_in_channel == 0)
@@ -1913,11 +1760,9 @@
if (ranks_in_channel != ranks)
return 0;
/* single slot */
- if (info->populated_ranks[channel][0][0] !=
- info->populated_ranks[channel][1][0])
+ if (info->populated_ranks[channel][0][0] != info->populated_ranks[channel][1][0])
return 1;
- if (info->populated_ranks[channel][0][1] !=
- info->populated_ranks[channel][1][1])
+ if (info->populated_ranks[channel][0][1] != info->populated_ranks[channel][1][1])
return 1;
if (info->is_x16_module[channel][0] != info->is_x16_module[channel][1])
return 0;
@@ -1930,37 +1775,33 @@
{
int i, channel, slot, rank, lane;
for (i = 0; i < 2; i++)
- FOR_ALL_RANKS(channel, slot, rank) {
- FOR_EACH_LANE_WITH_ECC(lane) {
- info->training.
- lane_timings[0][i][slot][rank][lane]
- = 32;
+ FOR_ALL_RANKS(channel, slot, rank)
+ {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
+ info->training.lane_timings[0][i][slot][rank][lane] = 32;
}
}
for (i = 1; i < 4; i++) {
- FOR_ALL_RANKS(channel, slot, rank) {
- FOR_EACH_LANE_WITH_ECC(lane) {
- info->training.
- lane_timings[i][channel]
- [slot][rank][lane] =
+ FOR_ALL_RANKS(channel, slot, rank)
+ {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
+ info->training.lane_timings[i][channel][slot][rank][lane] =
read_500(info, channel,
- get_timing_register_addr
- (lane, i, slot,
- rank), 9)
- + (i == 1) * 11; // !!!!
+ get_timing_register_addr(lane, i, slot, rank),
+ 9)
+ + (i == 1) * 11; // !!!!
}
}
}
-
}
static u32 get_etalon2(int flip, u32 addr)
{
- const u16 invmask[] = {
- 0xaaaa, 0x6db6, 0x4924, 0xeeee, 0xcccc, 0x8888, 0x7bde, 0x739c,
- 0x6318, 0x4210, 0xefbe, 0xcf3c, 0x8e38, 0x0c30, 0x0820
- };
+ const u16 invmask[] = {0xaaaa, 0x6db6, 0x4924, 0xeeee, 0xcccc, 0x8888, 0x7bde, 0x739c,
+ 0x6318, 0x4210, 0xefbe, 0xcf3c, 0x8e38, 0x0c30, 0x0820};
u32 ret;
u32 comp4 = addr / 480;
addr %= 480;
@@ -1980,7 +1821,7 @@
static void disable_cache(void)
{
- msr_t msr = {.lo = 0, .hi = 0 };
+ msr_t msr = {.lo = 0, .hi = 0};
wrmsr(MTRR_PHYS_BASE(3), msr);
wrmsr(MTRR_PHYS_MASK(3), msr);
@@ -1992,8 +1833,7 @@
msr.lo = base | MTRR_TYPE_WRPROT;
msr.hi = 0;
wrmsr(MTRR_PHYS_BASE(3), msr);
- msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRR_DEF_TYPE_EN)
- & 0xffffffff);
+ msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRR_DEF_TYPE_EN) & 0xffffffff);
msr.hi = 0x0000000f;
wrmsr(MTRR_PHYS_MASK(3), msr);
}
@@ -2039,7 +1879,7 @@
u8 failmask = 0;
int i;
int comp1, comp2, comp3;
- u32 failxor[2] = { 0, 0 };
+ u32 failxor[2] = {0, 0};
enable_cache((total_rank << 28), 1728 * 5 * 4);
@@ -2047,18 +1887,12 @@
for (comp1 = 0; comp1 < 4; comp1++)
for (comp2 = 0; comp2 < 60; comp2++) {
u32 re[4];
- u32 curroffset =
- comp3 * 8 * 60 + 2 * comp1 + 8 * comp2;
- read128((total_rank << 28) | (curroffset << 3),
- (u64 *) re);
- failxor[0] |=
- get_etalon2(flip, curroffset) ^ re[0];
- failxor[1] |=
- get_etalon2(flip, curroffset) ^ re[1];
- failxor[0] |=
- get_etalon2(flip, curroffset | 1) ^ re[2];
- failxor[1] |=
- get_etalon2(flip, curroffset | 1) ^ re[3];
+ u32 curroffset = comp3 * 8 * 60 + 2 * comp1 + 8 * comp2;
+ read128((total_rank << 28) | (curroffset << 3), (u64 *)re);
+ failxor[0] |= get_etalon2(flip, curroffset) ^ re[0];
+ failxor[1] |= get_etalon2(flip, curroffset) ^ re[1];
+ failxor[0] |= get_etalon2(flip, curroffset | 1) ^ re[2];
+ failxor[1] |= get_etalon2(flip, curroffset | 1) ^ re[3];
}
for (i = 0; i < 8; i++)
if ((0xff << (8 * (i % 4))) & failxor[i / 4])
@@ -2070,19 +1904,16 @@
}
const u32 seed1[0x18] = {
- 0x3a9d5ab5, 0x576cb65b, 0x555773b6, 0x2ab772ee,
- 0x555556ee, 0x3a9d5ab5, 0x576cb65b, 0x555773b6,
- 0x2ab772ee, 0x555556ee, 0x5155a555, 0x5155a555,
- 0x5155a555, 0x5155a555, 0x3a9d5ab5, 0x576cb65b,
- 0x555773b6, 0x2ab772ee, 0x555556ee, 0x55d6b4a5,
- 0x366d6b3a, 0x2ae5ddbb, 0x3b9ddbb7, 0x55d6b4a5,
+ 0x3a9d5ab5, 0x576cb65b, 0x555773b6, 0x2ab772ee, 0x555556ee, 0x3a9d5ab5,
+ 0x576cb65b, 0x555773b6, 0x2ab772ee, 0x555556ee, 0x5155a555, 0x5155a555,
+ 0x5155a555, 0x5155a555, 0x3a9d5ab5, 0x576cb65b, 0x555773b6, 0x2ab772ee,
+ 0x555556ee, 0x55d6b4a5, 0x366d6b3a, 0x2ae5ddbb, 0x3b9ddbb7, 0x55d6b4a5,
};
static u32 get_seed2(int a, int b)
{
const u32 seed2[5] = {
- 0x55555555, 0x33333333, 0x2e555a55, 0x55555555,
- 0x5b6db6db,
+ 0x55555555, 0x33333333, 0x2e555a55, 0x55555555, 0x5b6db6db,
};
u32 r;
r = seed2[(a + (a >= 10)) / 5];
@@ -2092,10 +1923,9 @@
static int make_shift(int comp2, int comp5, int x)
{
const u8 seed3[32] = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x38, 0x1c, 0x3c, 0x18, 0x38, 0x38,
- 0x38, 0x38, 0x38, 0x38, 0x0f, 0x0f, 0x0f, 0x0f,
- 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
+ 0x1c, 0x3c, 0x18, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x0f, 0x0f,
+ 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
};
return (comp2 - ((seed3[comp5] >> (x & 7)) & 1)) & 0x1f;
@@ -2114,37 +1944,32 @@
u32 part2;
int byte;
- part2 =
- ((seed1[comp5] >>
- make_shift(comp2, comp5,
- (comp3 >> 3) | (comp1 << 2) | 2)) & 1) ^ flip;
- part1 =
- ((seed1[comp5] >>
- make_shift(comp2, comp5,
- (comp3 >> 3) | (comp1 << 2) | 0)) & 1) ^ flip;
+ part2 = ((seed1[comp5] >> make_shift(comp2, comp5, (comp3 >> 3) | (comp1 << 2) | 2))
+ & 1)
+ ^ flip;
+ part1 = ((seed1[comp5] >> make_shift(comp2, comp5, (comp3 >> 3) | (comp1 << 2) | 0))
+ & 1)
+ ^ flip;
for (byte = 0; byte < 4; byte++)
- if ((get_seed2(comp5, comp4) >>
- make_shift(comp2, comp5, (byte | (comp1 << 2)))) & 1)
+ if ((get_seed2(comp5, comp4) >> make_shift(comp2, comp5, (byte | (comp1 << 2))))
+ & 1)
mask_byte |= 0xff << (8 * byte);
- return (mask_bit & mask_byte) | (part1 << comp3) | (part2 <<
- (comp3 + 16));
+ return (mask_bit & mask_byte) | (part1 << comp3) | (part2 << (comp3 + 16));
}
-static void
-write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
- char flip)
+static void write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
+ char flip)
{
int i;
for (i = 0; i < 2048; i++)
- write32p((totalrank << 28) | (region << 25) | (block << 16) |
- (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
+ write32p((totalrank << 28) | (region << 25) | (block << 16) | (i << 2),
+ get_etalon(flip, (block << 16) | (i << 2)));
}
-static u8
-check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
- char flip)
+static u8 check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
+ char flip)
{
u8 failmask = 0;
u32 failxor[2];
@@ -2158,13 +1983,9 @@
for (comp3 = 0; comp3 < 2 && failmask != 0xff; comp3++) {
for (comp1 = 0; comp1 < 16; comp1++)
for (comp2 = 0; comp2 < 64; comp2++) {
- u32 addr =
- (totalrank << 28) | (region << 25) | (block
- << 16)
- | (comp3 << 12) | (comp2 << 6) | (comp1 <<
- 2);
- failxor[comp1 & 1] |=
- read32p(addr) ^ get_etalon(flip, addr);
+ u32 addr = (totalrank << 28) | (region << 25) | (block << 16)
+ | (comp3 << 12) | (comp2 << 6) | (comp1 << 2);
+ failxor[comp1 & 1] |= read32p(addr) ^ get_etalon(flip, addr);
}
for (i = 0; i < 8; i++)
if ((0xff << (8 * (i % 4))) & failxor[i / 4])
@@ -2185,9 +2006,7 @@
return 1;
}
-enum state {
- BEFORE_USABLE = 0, AT_USABLE = 1, AT_MARGIN = 2, COMPLETE = 3
-};
+enum state { BEFORE_USABLE = 0, AT_USABLE = 1, AT_MARGIN = 2, COMPLETE = 3 };
static int validate_state(enum state *in)
{
@@ -2198,14 +2017,13 @@
return 1;
}
-static void
-do_fsm(enum state *state, u16 *counter,
- u8 fail_mask, int margin, int uplimit,
- u8 *res_low, u8 *res_high, u8 val)
+static void do_fsm(enum state *state, u16 *counter, u8 fail_mask, int margin, int uplimit,
+ u8 *res_low, u8 *res_high, u8 val)
{
int lane;
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
int is_fail = (fail_mask >> lane) & 1;
switch (state[lane]) {
case BEFORE_USABLE:
@@ -2250,10 +2068,9 @@
}
}
-static void
-train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank,
- u8 total_rank, u8 reg_178, int first_run, int niter,
- timing_bounds_t * timings)
+static void train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank,
+ u8 total_rank, u8 reg_178, int first_run, int niter,
+ timing_bounds_t *timings)
{
int lane;
enum state state[8];
@@ -2269,15 +2086,12 @@
if (!first_run) {
int is_all_ok = 1;
- FOR_EACH_LANE(lane) {
- if (timings[reg_178][channel][slot][rank][lane].
- smallest ==
- timings[reg_178][channel][slot][rank][lane].
- largest) {
- timings[reg_178][channel][slot][rank][lane].
- smallest = 0;
- timings[reg_178][channel][slot][rank][lane].
- largest = 0;
+ FOR_EACH_LANE(lane)
+ {
+ if (timings[reg_178][channel][slot][rank][lane].smallest
+ == timings[reg_178][channel][slot][rank][lane].largest) {
+ timings[reg_178][channel][slot][rank][lane].smallest = 0;
+ timings[reg_178][channel][slot][rank][lane].largest = 0;
is_all_ok = 0;
}
}
@@ -2293,54 +2107,46 @@
write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1);
failmask = check_testing(info, total_rank, 0);
MCHBAR32_OR(0xfb0, 0x00030000);
- do_fsm(state, count, failmask, 5, 47, lower_usable,
- upper_usable, reg1b3);
+ do_fsm(state, count, failmask, 5, 47, lower_usable, upper_usable, reg1b3);
}
if (reg1b3) {
write_1d0(0, 0x1b3, 6, 1);
write_1d0(0, 0x1a3, 6, 1);
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
if (state[lane] == COMPLETE) {
- timings[reg_178][channel][slot][rank][lane].
- smallest =
- lower_usable[lane] +
- (info->training.
- lane_timings[0][channel][slot][rank][lane]
- & 0x3F) - 32;
- timings[reg_178][channel][slot][rank][lane].
- largest =
- upper_usable[lane] +
- (info->training.
- lane_timings[0][channel][slot][rank][lane]
- & 0x3F) - 32;
+ timings[reg_178][channel][slot][rank][lane].smallest =
+ lower_usable[lane]
+ + (info->training
+ .lane_timings[0][channel][slot][rank][lane]
+ & 0x3F)
+ - 32;
+ timings[reg_178][channel][slot][rank][lane].largest =
+ upper_usable[lane]
+ + (info->training
+ .lane_timings[0][channel][slot][rank][lane]
+ & 0x3F)
+ - 32;
}
}
}
if (!first_run) {
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
if (state[lane] == COMPLETE) {
write_500(info, channel,
- timings[reg_178][channel][slot][rank]
- [lane].smallest,
- get_timing_register_addr(lane, 0,
- slot, rank),
- 9, 1);
- write_500(info, channel,
- timings[reg_178][channel][slot][rank]
- [lane].smallest +
- info->training.
- lane_timings[1][channel][slot][rank]
- [lane]
- -
- info->training.
- lane_timings[0][channel][slot][rank]
- [lane], get_timing_register_addr(lane,
- 1,
- slot,
- rank),
- 9, 1);
+ timings[reg_178][channel][slot][rank][lane].smallest,
+ get_timing_register_addr(lane, 0, slot, rank), 9, 1);
+ write_500(
+ info, channel,
+ timings[reg_178][channel][slot][rank][lane].smallest
+ + info->training.lane_timings[1][channel][slot]
+ [rank][lane]
+ - info->training.lane_timings[0][channel][slot]
+ [rank][lane],
+ get_timing_register_addr(lane, 1, slot, rank), 9, 1);
num_successfully_checked[lane] = 0;
} else
num_successfully_checked[lane] = -1;
@@ -2350,98 +2156,69 @@
for (i = 0; i < niter; i++) {
if (failmask == 0xFF)
break;
- failmask |=
- check_testing_type2(info, total_rank, 2, i,
- 0);
- failmask |=
- check_testing_type2(info, total_rank, 3, i,
- 1);
+ failmask |= check_testing_type2(info, total_rank, 2, i, 0);
+ failmask |= check_testing_type2(info, total_rank, 3, i, 1);
}
MCHBAR32_OR(0xfb0, 0x00030000);
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
if (num_successfully_checked[lane] != 0xffff) {
if ((1 << lane) & failmask) {
- if (timings[reg_178][channel]
- [slot][rank][lane].
- largest <=
- timings[reg_178][channel]
- [slot][rank][lane].smallest)
- num_successfully_checked
- [lane] = -1;
+ if (timings[reg_178][channel][slot][rank][lane]
+ .largest
+ <= timings[reg_178][channel][slot][rank]
+ [lane]
+ .smallest)
+ num_successfully_checked[lane] = -1;
else {
- num_successfully_checked
- [lane] = 0;
- timings[reg_178]
- [channel][slot]
- [rank][lane].
- smallest++;
+ num_successfully_checked[lane] = 0;
+ timings[reg_178][channel][slot][rank]
+ [lane]
+ .smallest++;
write_500(info, channel,
- timings
- [reg_178]
- [channel]
- [slot][rank]
- [lane].
- smallest,
- get_timing_register_addr
- (lane, 0,
- slot, rank),
+ timings[reg_178][channel]
+ [slot][rank][lane]
+ .smallest,
+ get_timing_register_addr(
+ lane, 0, slot, rank),
9, 1);
- write_500(info, channel,
- timings
- [reg_178]
- [channel]
- [slot][rank]
- [lane].
- smallest +
- info->
- training.
- lane_timings
- [1][channel]
- [slot][rank]
- [lane]
- -
- info->
- training.
- lane_timings
- [0][channel]
- [slot][rank]
- [lane],
- get_timing_register_addr
- (lane, 1,
- slot, rank),
- 9, 1);
+ write_500(
+ info, channel,
+ timings[reg_178][channel][slot]
+ [rank][lane]
+ .smallest
+ + info->training.lane_timings
+ [1][channel]
+ [slot][rank]
+ [lane]
+ - info->training.lane_timings
+ [0][channel]
+ [slot][rank]
+ [lane],
+ get_timing_register_addr(
+ lane, 1, slot, rank),
+ 9, 1);
}
} else
- num_successfully_checked[lane]
- ++;
+ num_successfully_checked[lane]++;
}
}
- }
- while (!check_bounded(num_successfully_checked, 2))
- ;
+ } while (!check_bounded(num_successfully_checked, 2));
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
if (state[lane] == COMPLETE) {
write_500(info, channel,
- timings[reg_178][channel][slot][rank]
- [lane].largest,
- get_timing_register_addr(lane, 0,
- slot, rank),
- 9, 1);
- write_500(info, channel,
- timings[reg_178][channel][slot][rank]
- [lane].largest +
- info->training.
- lane_timings[1][channel][slot][rank]
- [lane]
- -
- info->training.
- lane_timings[0][channel][slot][rank]
- [lane], get_timing_register_addr(lane,
- 1,
- slot,
- rank),
- 9, 1);
+ timings[reg_178][channel][slot][rank][lane].largest,
+ get_timing_register_addr(lane, 0, slot, rank), 9, 1);
+ write_500(
+ info, channel,
+ timings[reg_178][channel][slot][rank][lane].largest
+ + info->training.lane_timings[1][channel][slot]
+ [rank][lane]
+ - info->training.lane_timings[0][channel][slot]
+ [rank][lane],
+ get_timing_register_addr(lane, 1, slot, rank), 9, 1);
num_successfully_checked[lane] = 0;
} else
num_successfully_checked[lane] = -1;
@@ -2452,97 +2229,68 @@
for (i = 0; i < niter; i++) {
if (failmask == 0xFF)
break;
- failmask |=
- check_testing_type2(info, total_rank, 2, i,
- 0);
- failmask |=
- check_testing_type2(info, total_rank, 3, i,
- 1);
+ failmask |= check_testing_type2(info, total_rank, 2, i, 0);
+ failmask |= check_testing_type2(info, total_rank, 3, i, 1);
}
MCHBAR32_OR(0xfb0, 0x00030000);
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
if (num_successfully_checked[lane] != 0xffff) {
if ((1 << lane) & failmask) {
- if (timings[reg_178][channel]
- [slot][rank][lane].
- largest <=
- timings[reg_178][channel]
- [slot][rank][lane].
- smallest) {
- num_successfully_checked
- [lane] = -1;
+ if (timings[reg_178][channel][slot][rank][lane]
+ .largest
+ <= timings[reg_178][channel][slot][rank]
+ [lane]
+ .smallest) {
+ num_successfully_checked[lane] = -1;
} else {
- num_successfully_checked
- [lane] = 0;
- timings[reg_178]
- [channel][slot]
- [rank][lane].
- largest--;
+ num_successfully_checked[lane] = 0;
+ timings[reg_178][channel][slot][rank]
+ [lane]
+ .largest--;
write_500(info, channel,
- timings
- [reg_178]
- [channel]
- [slot][rank]
- [lane].
- largest,
- get_timing_register_addr
- (lane, 0,
- slot, rank),
+ timings[reg_178][channel]
+ [slot][rank][lane]
+ .largest,
+ get_timing_register_addr(
+ lane, 0, slot, rank),
9, 1);
- write_500(info, channel,
- timings
- [reg_178]
- [channel]
- [slot][rank]
- [lane].
- largest +
- info->
- training.
- lane_timings
- [1][channel]
- [slot][rank]
- [lane]
- -
- info->
- training.
- lane_timings
- [0][channel]
- [slot][rank]
- [lane],
- get_timing_register_addr
- (lane, 1,
- slot, rank),
- 9, 1);
+ write_500(
+ info, channel,
+ timings[reg_178][channel][slot]
+ [rank][lane]
+ .largest
+ + info->training.lane_timings
+ [1][channel]
+ [slot][rank]
+ [lane]
+ - info->training.lane_timings
+ [0][channel]
+ [slot][rank]
+ [lane],
+ get_timing_register_addr(
+ lane, 1, slot, rank),
+ 9, 1);
}
} else
- num_successfully_checked[lane]
- ++;
+ num_successfully_checked[lane]++;
}
}
- }
- while (!check_bounded(num_successfully_checked, 3))
- ;
+ } while (!check_bounded(num_successfully_checked, 3));
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
write_500(info, channel,
- info->training.
- lane_timings[0][channel][slot][rank][lane],
- get_timing_register_addr(lane, 0, slot, rank),
- 9, 1);
+ info->training.lane_timings[0][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 0, slot, rank), 9, 1);
write_500(info, channel,
- info->training.
- lane_timings[1][channel][slot][rank][lane],
- get_timing_register_addr(lane, 1, slot, rank),
- 9, 1);
- if (timings[reg_178][channel][slot][rank][lane].
- largest <=
- timings[reg_178][channel][slot][rank][lane].
- smallest) {
- timings[reg_178][channel][slot][rank][lane].
- largest = 0;
- timings[reg_178][channel][slot][rank][lane].
- smallest = 0;
+ info->training.lane_timings[1][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 1, slot, rank), 9, 1);
+ if (timings[reg_178][channel][slot][rank][lane].largest
+ <= timings[reg_178][channel][slot][rank][lane].smallest) {
+ timings[reg_178][channel][slot][rank][lane].largest = 0;
+ timings[reg_178][channel][slot][rank][lane].smallest = 0;
}
}
}
@@ -2559,12 +2307,13 @@
write_1d0(val, 0x10b, 6, 1);
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
- FOR_EACH_LANE_WITH_ECC(lane) {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
u16 reg_500;
reg_500 = read_500(info, channel,
- get_timing_register_addr(lane, 0, slot,
- rank), 9);
+ get_timing_register_addr(lane, 0, slot, rank), 9);
if (val == 1) {
if (lut16[info->clock_speed_index] <= reg_500)
reg_500 -= lut16[info->clock_speed_index];
@@ -2582,7 +2331,8 @@
static void set_ecc(int onoff)
{
int channel;
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
u8 t;
t = MCHBAR8((channel << 10) + 0x5f8);
if (onoff)
@@ -2603,24 +2353,21 @@
write_1d0(2 * val, 0x178, 7, 1);
}
-static void
-write_500_timings_type(struct raminfo *info, int channel, int slot, int rank,
- int type)
+static void write_500_timings_type(struct raminfo *info, int channel, int slot, int rank,
+ int type)
{
int lane;
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
write_500(info, channel,
- info->training.
- lane_timings[type][channel][slot][rank][lane],
- get_timing_register_addr(lane, type, slot, rank), 9,
- 0);
+ info->training.lane_timings[type][channel][slot][rank][lane],
+ get_timing_register_addr(lane, type, slot, rank), 9, 0);
}
}
-static void
-try_timing_offsets(struct raminfo *info, int channel,
- int slot, int rank, int totalrank)
+static void try_timing_offsets(struct raminfo *info, int channel, int slot, int rank,
+ int totalrank)
{
u16 count[8];
enum state state[8];
@@ -2635,15 +2382,14 @@
memset(count, 0, sizeof(count));
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
write_500(info, channel,
- info->training.
- lane_timings[2][channel][slot][rank][lane] + 32,
+ info->training.lane_timings[2][channel][slot][rank][lane] + 32,
get_timing_register_addr(lane, 3, slot, rank), 9, 1);
}
- for (timing_offset = 0; !validate_state(state) && timing_offset < 64;
- timing_offset++) {
+ for (timing_offset = 0; !validate_state(state) && timing_offset < 64; timing_offset++) {
u8 failmask;
write_1d0(timing_offset ^ 32, 0x1bb, 6, 1);
failmask = 0;
@@ -2652,15 +2398,16 @@
write_testing(info, totalrank, flip);
failmask |= check_testing(info, totalrank, flip);
}
- do_fsm(state, count, failmask, 10, 63, lower_usable,
- upper_usable, timing_offset);
+ do_fsm(state, count, failmask, 10, 63, lower_usable, upper_usable,
+ timing_offset);
}
write_1d0(0, 0x1bb, 6, 1);
dump_timings(info);
if (!validate_state(state))
die("Couldn't discover DRAM timings (1)\n");
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
u8 bias = 0;
if (info->silicon_revision) {
@@ -2674,24 +2421,22 @@
}
}
write_500(info, channel,
- info->training.
- lane_timings[2][channel][slot][rank][lane] +
- (upper_usable[lane] + lower_usable[lane]) / 2 - bias,
+ info->training.lane_timings[2][channel][slot][rank][lane]
+ + (upper_usable[lane] + lower_usable[lane]) / 2 - bias,
get_timing_register_addr(lane, 3, slot, rank), 9, 1);
info->training.timing2_bounds[channel][slot][rank][lane][0] =
- info->training.lane_timings[2][channel][slot][rank][lane] +
- lower_usable[lane];
+ info->training.lane_timings[2][channel][slot][rank][lane]
+ + lower_usable[lane];
info->training.timing2_bounds[channel][slot][rank][lane][1] =
- info->training.lane_timings[2][channel][slot][rank][lane] +
- upper_usable[lane];
+ info->training.lane_timings[2][channel][slot][rank][lane]
+ + upper_usable[lane];
info->training.timing2_offset[channel][slot][rank][lane] =
- info->training.lane_timings[2][channel][slot][rank][lane];
+ info->training.lane_timings[2][channel][slot][rank][lane];
}
}
-static u8
-choose_training(struct raminfo *info, int channel, int slot, int rank,
- int lane, timing_bounds_t * timings, u8 center_178)
+static u8 choose_training(struct raminfo *info, int channel, int slot, int rank, int lane,
+ timing_bounds_t *timings, u8 center_178)
{
u16 central_weight;
u16 side_weight;
@@ -2707,18 +2452,15 @@
if (info->silicon_revision == 1 && channel == 1) {
central_weight = 5;
side_weight = 20;
- if ((info->
- populated_ranks_mask[1] ^ (info->
- populated_ranks_mask[1] >> 2)) &
- 1)
+ if ((info->populated_ranks_mask[1] ^ (info->populated_ranks_mask[1] >> 2)) & 1)
span = 18;
}
if ((info->populated_ranks_mask[0] & 5) == 5) {
central_weight = 20;
side_weight = 20;
}
- if (info->clock_speed_index >= 2
- && (info->populated_ranks_mask[0] & 5) == 5 && slot == 1) {
+ if (info->clock_speed_index >= 2 && (info->populated_ranks_mask[0] & 5) == 5
+ && slot == 1) {
if (info->silicon_revision == 1) {
switch (channel) {
case 0:
@@ -2740,8 +2482,7 @@
central_weight = 20;
}
}
- for (reg_178 = center_178 - span; reg_178 <= center_178 + span;
- reg_178 += span) {
+ for (reg_178 = center_178 - span; reg_178 <= center_178 + span; reg_178 += span) {
u8 smallest;
u8 largest;
largest = timings[reg_178][channel][slot][rank][lane].largest;
@@ -2760,10 +2501,8 @@
if (count == 0)
die("Couldn't discover DRAM timings (2)\n");
result = sum / (2 * count);
- lower_margin =
- result - timings[center_178][channel][slot][rank][lane].smallest;
- upper_margin =
- timings[center_178][channel][slot][rank][lane].largest - result;
+ lower_margin = result - timings[center_178][channel][slot][rank][lane].smallest;
+ upper_margin = timings[center_178][channel][slot][rank][lane].largest - result;
if (upper_margin < 10 && lower_margin > 10)
result -= min(lower_margin - 10, 10 - upper_margin);
if (upper_margin > 10 && lower_margin < 10)
@@ -2773,7 +2512,7 @@
#define STANDARD_MIN_MARGIN 5
-static u8 choose_reg178(struct raminfo *info, timing_bounds_t * timings)
+static u8 choose_reg178(struct raminfo *info, timing_bounds_t *timings)
{
u16 margin[64];
int lane, rank, slot, channel;
@@ -2784,12 +2523,14 @@
reg178 < reg178_max[info->clock_speed_index];
reg178 += reg178_step[info->clock_speed_index]) {
margin[reg178] = -1;
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
- FOR_EACH_LANE(lane) {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
+ FOR_EACH_LANE(lane)
+ {
int curmargin =
- timings[reg178][channel][slot][rank][lane].largest -
- timings[reg178][channel][slot][rank][lane].
- smallest + 1;
+ timings[reg178][channel][slot][rank][lane].largest
+ - timings[reg178][channel][slot][rank][lane].smallest
+ + 1;
if (curmargin < margin[reg178])
margin[reg178] = curmargin;
}
@@ -2814,18 +2555,14 @@
reg178 < reg178_max[info->clock_speed_index];
reg178 += reg178_step[info->clock_speed_index])
if (margin[reg178] >= threshold) {
- usable_length +=
- reg178_step[info->clock_speed_index];
+ usable_length += reg178_step[info->clock_speed_index];
info->training.reg178_largest =
- reg178 -
- 2 * reg178_step[info->clock_speed_index];
+ reg178 - 2 * reg178_step[info->clock_speed_index];
if (!smallest_fount) {
smallest_fount = 1;
info->training.reg178_smallest =
- reg178 +
- reg178_step[info->
- clock_speed_index];
+ reg178 + reg178_step[info->clock_speed_index];
}
}
if (usable_length >= 0x21)
@@ -2844,24 +2581,19 @@
if (!info->cached_training)
return 0;
- FOR_ALL_RANKS(channel, slot, rank) {
+ FOR_ALL_RANKS(channel, slot, rank)
+ {
for (lane = 0; lane < 8 + info->use_ecc; lane++) {
u16 cached_value, estimation_value;
- cached_value =
- info->cached_training->
- lane_timings[1][channel][slot][rank]
- [lane];
- if (cached_value >= 0x18
- && cached_value <= 0x1E7) {
+ cached_value = info->cached_training
+ ->lane_timings[1][channel][slot][rank][lane];
+ if (cached_value >= 0x18 && cached_value <= 0x1E7) {
estimation_value =
- info->training.
- lane_timings[1][channel]
- [slot][rank][lane];
- if (estimation_value <
- cached_value - 24)
+ info->training
+ .lane_timings[1][channel][slot][rank][lane];
+ if (estimation_value < cached_value - 24)
return 0;
- if (estimation_value >
- cached_value + 24)
+ if (estimation_value > cached_value + 24)
return 0;
}
}
@@ -2884,11 +2616,9 @@
info->training.reg178_center = info->cached_training->reg178_center;
info->training.reg178_smallest = info->cached_training->reg178_smallest;
info->training.reg178_largest = info->cached_training->reg178_largest;
- memcpy(&info->training.timing_bounds,
- &info->cached_training->timing_bounds,
+ memcpy(&info->training.timing_bounds, &info->cached_training->timing_bounds,
sizeof(info->training.timing_bounds));
- memcpy(&info->training.timing_offset,
- &info->cached_training->timing_offset,
+ memcpy(&info->training.timing_offset, &info->cached_training->timing_offset,
sizeof(info->training.timing_offset));
write_1d0(2, 0x142, 3, 1);
@@ -2903,8 +2633,8 @@
for (tm = 0; tm < 2; tm++) {
int totalrank;
- set_178(tm ? info->cached_training->reg178_largest : info->
- cached_training->reg178_smallest);
+ set_178(tm ? info->cached_training->reg178_largest
+ : info->cached_training->reg178_smallest);
totalrank = 0;
/* Check timing ranges. With i == 0 we check smallest one and with
@@ -2912,59 +2642,60 @@
it still works whereas with j == 1 we check that just outside of
bound we fail.
*/
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
for (i = 0; i < 2; i++) {
- FOR_EACH_LANE(lane) {
+ FOR_EACH_LANE(lane)
+ {
write_500(info, channel,
- info->cached_training->
- timing2_bounds[channel][slot]
- [rank][lane][i],
- get_timing_register_addr(lane,
- 3,
- slot,
- rank),
+ info->cached_training
+ ->timing2_bounds[channel][slot][rank]
+ [lane][i],
+ get_timing_register_addr(lane, 3, slot, rank),
9, 1);
if (!i)
- write_500(info, channel,
- info->
- cached_training->
- timing2_offset
- [channel][slot][rank]
- [lane],
- get_timing_register_addr
- (lane, 2, slot, rank),
- 9, 1);
+ write_500(
+ info, channel,
+ info->cached_training
+ ->timing2_offset[channel][slot]
+ [rank][lane],
+ get_timing_register_addr(lane, 2, slot,
+ rank),
+ 9, 1);
write_500(info, channel,
- i ? info->cached_training->
- timing_bounds[tm][channel]
- [slot][rank][lane].
- largest : info->
- cached_training->
- timing_bounds[tm][channel]
- [slot][rank][lane].smallest,
- get_timing_register_addr(lane,
- 0,
- slot,
- rank),
+ i ? info->cached_training
+ ->timing_bounds[tm][channel]
+ [slot][rank]
+ [lane]
+ .largest
+ : info->cached_training
+ ->timing_bounds[tm][channel]
+ [slot][rank]
+ [lane]
+ .smallest,
+ get_timing_register_addr(lane, 0, slot, rank),
9, 1);
- write_500(info, channel,
- info->cached_training->
- timing_offset[channel][slot]
- [rank][lane] +
- (i ? info->cached_training->
- timing_bounds[tm][channel]
- [slot][rank][lane].
- largest : info->
- cached_training->
- timing_bounds[tm][channel]
- [slot][rank][lane].
- smallest) - 64,
- get_timing_register_addr(lane,
- 1,
- slot,
- rank),
- 9, 1);
+ write_500(
+ info, channel,
+ info->cached_training
+ ->timing_offset[channel][slot]
+ [rank][lane]
+ + (i ? info->cached_training
+ ->timing_bounds
+ [tm][channel]
+ [slot][rank]
+ [lane]
+ .largest
+ : info->cached_training
+ ->timing_bounds
+ [tm][channel]
+ [slot][rank]
+ [lane]
+ .smallest)
+ - 64,
+ get_timing_register_addr(lane, 1, slot, rank),
+ 9, 1);
}
for (j = 0; j < 2; j++) {
u8 failmask;
@@ -2972,19 +2703,15 @@
char reg1b3;
reg1b3 = (j == 1) + 4;
- reg1b3 =
- j == i ? reg1b3 : (-reg1b3) & 0x3f;
+ reg1b3 = j == i ? reg1b3 : (-reg1b3) & 0x3f;
write_1d0(reg1b3, 0x1bb, 6, 1);
write_1d0(reg1b3, 0x1b3, 6, 1);
write_1d0(reg1b3, 0x1a3, 6, 1);
flip = !flip;
write_testing(info, totalrank, flip);
- failmask =
- check_testing(info, totalrank,
- flip);
- expected_failmask =
- j == 0 ? 0x00 : 0xff;
+ failmask = check_testing(info, totalrank, flip);
+ expected_failmask = j == 0 ? 0x00 : 0xff;
if (failmask != expected_failmask)
goto fail;
}
@@ -3009,7 +2736,8 @@
return 1;
fail:
- FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank)
+ {
write_500_timings_type(info, channel, slot, rank, 1);
write_500_timings_type(info, channel, slot, rank, 2);
write_500_timings_type(info, channel, slot, rank, 3);
@@ -3053,7 +2781,8 @@
}
set_ecc(0);
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
int i;
write_500_timings_type(info, channel, slot, rank, 0);
@@ -3067,145 +2796,130 @@
totalrank++;
}
- if (reg178_min[info->clock_speed_index] <
- reg178_max[info->clock_speed_index])
+ if (reg178_min[info->clock_speed_index] < reg178_max[info->clock_speed_index])
memset(timings[reg178_min[info->clock_speed_index]], 0,
- sizeof(timings[0]) *
- (reg178_max[info->clock_speed_index] -
- reg178_min[info->clock_speed_index]));
+ sizeof(timings[0])
+ * (reg178_max[info->clock_speed_index]
+ - reg178_min[info->clock_speed_index]));
for (reg_178 = reg178_min[info->clock_speed_index];
reg_178 < reg178_max[info->clock_speed_index];
reg_178 += reg178_step[info->clock_speed_index]) {
totalrank = 0;
set_178(reg_178);
- FOR_EACH_CHANNEL_BACKWARDS(channel) {
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
- memset(&timings[reg_178][channel][slot]
- [rank][0].smallest, 0, 16);
- if (info->
- populated_ranks[channel][slot]
- [rank]) {
- train_ram_at_178(info, channel,
- slot, rank,
- totalrank,
- reg_178, 1,
- niter,
- timings);
- totalrank++;
- }
+ FOR_EACH_CHANNEL_BACKWARDS(channel)
+ {
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank)
+ {
+ memset(&timings[reg_178][channel][slot][rank][0].smallest, 0,
+ 16);
+ if (info->populated_ranks[channel][slot][rank]) {
+ train_ram_at_178(info, channel, slot, rank, totalrank,
+ reg_178, 1, niter, timings);
+ totalrank++;
+ }
}
}
}
reg178_center = choose_reg178(info, timings);
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
- FOR_EACH_LANE(lane) {
- info->training.timing_bounds[0][channel][slot][rank][lane].
- smallest =
- timings[info->training.
- reg178_smallest][channel][slot][rank][lane].
- smallest;
- info->training.timing_bounds[0][channel][slot][rank][lane].
- largest =
- timings[info->training.
- reg178_smallest][channel][slot][rank][lane].largest;
- info->training.timing_bounds[1][channel][slot][rank][lane].
- smallest =
- timings[info->training.
- reg178_largest][channel][slot][rank][lane].smallest;
- info->training.timing_bounds[1][channel][slot][rank][lane].
- largest =
- timings[info->training.
- reg178_largest][channel][slot][rank][lane].largest;
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
+ FOR_EACH_LANE(lane)
+ {
+ info->training.timing_bounds[0][channel][slot][rank][lane].smallest =
+ timings[info->training.reg178_smallest][channel][slot][rank]
+ [lane]
+ .smallest;
+ info->training.timing_bounds[0][channel][slot][rank][lane].largest =
+ timings[info->training.reg178_smallest][channel][slot][rank]
+ [lane]
+ .largest;
+ info->training.timing_bounds[1][channel][slot][rank][lane].smallest =
+ timings[info->training.reg178_largest][channel][slot][rank]
+ [lane]
+ .smallest;
+ info->training.timing_bounds[1][channel][slot][rank][lane].largest =
+ timings[info->training.reg178_largest][channel][slot][rank]
+ [lane]
+ .largest;
info->training.timing_offset[channel][slot][rank][lane] =
info->training.lane_timings[1][channel][slot][rank][lane]
- -
- info->training.lane_timings[0][channel][slot][rank][lane] +
- 64;
+ - info->training.lane_timings[0][channel][slot][rank][lane]
+ + 64;
}
}
if (info->silicon_revision == 1
- && (info->
- populated_ranks_mask[1] ^ (info->
- populated_ranks_mask[1] >> 2)) & 1) {
+ && (info->populated_ranks_mask[1] ^ (info->populated_ranks_mask[1] >> 2)) & 1) {
int ranks_after_channel1;
totalrank = 0;
- for (reg_178 = reg178_center - 18;
- reg_178 <= reg178_center + 18; reg_178 += 18) {
+ for (reg_178 = reg178_center - 18; reg_178 <= reg178_center + 18;
+ reg_178 += 18) {
totalrank = 0;
set_178(reg_178);
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
- if (info->
- populated_ranks[1][slot][rank]) {
- train_ram_at_178(info, 1, slot,
- rank,
- totalrank,
- reg_178, 0,
- niter,
- timings);
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank)
+ {
+ if (info->populated_ranks[1][slot][rank]) {
+ train_ram_at_178(info, 1, slot, rank, totalrank,
+ reg_178, 0, niter, timings);
totalrank++;
}
}
}
ranks_after_channel1 = totalrank;
- for (reg_178 = reg178_center - 12;
- reg_178 <= reg178_center + 12; reg_178 += 12) {
+ for (reg_178 = reg178_center - 12; reg_178 <= reg178_center + 12;
+ reg_178 += 12) {
totalrank = ranks_after_channel1;
set_178(reg_178);
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
- if (info->
- populated_ranks[0][slot][rank]) {
- train_ram_at_178(info, 0, slot,
- rank,
- totalrank,
- reg_178, 0,
- niter,
- timings);
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank)
+ {
+ if (info->populated_ranks[0][slot][rank]) {
+ train_ram_at_178(info, 0, slot, rank, totalrank,
+ reg_178, 0, niter, timings);
totalrank++;
}
}
-
}
} else {
- for (reg_178 = reg178_center - 12;
- reg_178 <= reg178_center + 12; reg_178 += 12) {
+ for (reg_178 = reg178_center - 12; reg_178 <= reg178_center + 12;
+ reg_178 += 12) {
totalrank = 0;
set_178(reg_178);
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
- train_ram_at_178(info, channel, slot, rank,
- totalrank, reg_178, 0, niter,
- timings);
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
+ train_ram_at_178(info, channel, slot, rank, totalrank, reg_178,
+ 0, niter, timings);
totalrank++;
}
}
}
set_178(reg178_center);
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
- FOR_EACH_LANE(lane) {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
+ FOR_EACH_LANE(lane)
+ {
u16 tm0;
- tm0 =
- choose_training(info, channel, slot, rank, lane, timings,
- reg178_center);
+ tm0 = choose_training(info, channel, slot, rank, lane, timings,
+ reg178_center);
write_500(info, channel, tm0,
get_timing_register_addr(lane, 0, slot, rank), 9, 1);
- write_500(info, channel,
- tm0 +
- info->training.
- lane_timings[1][channel][slot][rank][lane] -
- info->training.
- lane_timings[0][channel][slot][rank][lane],
- get_timing_register_addr(lane, 1, slot, rank), 9, 1);
+ write_500(
+ info, channel,
+ tm0 + info->training.lane_timings[1][channel][slot][rank][lane]
+ - info->training
+ .lane_timings[0][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 1, slot, rank), 9, 1);
}
}
totalrank = 0;
- FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank)
+ {
try_timing_offsets(info, channel, slot, rank, totalrank);
totalrank++;
}
@@ -3275,10 +2989,9 @@
int freq_max_reduced;
};
-static void
-compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2,
- int num_cycles_2, int num_cycles_1, int round_it,
- int add_freqs, struct stru1 *result)
+static void compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2,
+ int num_cycles_2, int num_cycles_1, int round_it,
+ int add_freqs, struct stru1 *result)
{
int g;
int common_time_unit_ps;
@@ -3309,43 +3022,35 @@
result->divisor_f3_to_f1 = 0;
} else {
if (freq2_reduced < freq1_reduced) {
- result->freq3_to_2_remainder =
- result->freq3_to_2_remaindera =
- freq3 % freq1_reduced - freq1_reduced + 1;
- result->freq4_to_max_remainder =
- -(freq4 % freq1_reduced);
+ result->freq3_to_2_remainder = result->freq3_to_2_remaindera =
+ freq3 % freq1_reduced - freq1_reduced + 1;
+ result->freq4_to_max_remainder = -(freq4 % freq1_reduced);
result->divisor_f3_to_f1 = freq3 / freq1_reduced;
result->divisor_f4_to_f2 =
- (freq4 -
- (freq1_reduced - freq2_reduced)) / freq2_reduced;
+ (freq4 - (freq1_reduced - freq2_reduced)) / freq2_reduced;
result->freq4_to_2_remainder =
- -(char)((freq1_reduced - freq2_reduced) +
- ((u8) freq4 -
- (freq1_reduced -
- freq2_reduced)) % (u8) freq2_reduced);
+ -(char)((freq1_reduced - freq2_reduced)
+ + ((u8)freq4 - (freq1_reduced - freq2_reduced))
+ % (u8)freq2_reduced);
} else {
if (freq2_reduced > freq1_reduced) {
result->freq4_to_max_remainder =
- (freq4 % freq2_reduced) - freq2_reduced + 1;
+ (freq4 % freq2_reduced) - freq2_reduced + 1;
result->freq4_to_2_remainder =
- freq4 % freq_max_reduced -
- freq_max_reduced + 1;
+ freq4 % freq_max_reduced - freq_max_reduced + 1;
} else {
- result->freq4_to_max_remainder =
- -(freq4 % freq2_reduced);
+ result->freq4_to_max_remainder = -(freq4 % freq2_reduced);
result->freq4_to_2_remainder =
- -(char)(freq4 % freq_max_reduced);
+ -(char)(freq4 % freq_max_reduced);
}
result->divisor_f4_to_f2 = freq4 / freq2_reduced;
result->divisor_f3_to_f1 =
- (freq3 -
- (freq2_reduced - freq1_reduced)) / freq1_reduced;
+ (freq3 - (freq2_reduced - freq1_reduced)) / freq1_reduced;
result->freq3_to_2_remainder = -(freq3 % freq2_reduced);
result->freq3_to_2_remaindera =
- -(char)((freq_max_reduced - freq_min_reduced) +
- (freq3 -
- (freq_max_reduced -
- freq_min_reduced)) % freq1_reduced);
+ -(char)((freq_max_reduced - freq_min_reduced)
+ + (freq3 - (freq_max_reduced - freq_min_reduced))
+ % freq1_reduced);
}
}
result->divisor_f3_to_fmax = freq3 / freq_max_reduced;
@@ -3367,41 +3072,30 @@
result->freq_max_reduced = freq_max_reduced;
}
-static void
-set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
- int num_cycles_2, int num_cycles_1, int num_cycles_3,
- int num_cycles_4, int reverse)
+static void set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, int num_cycles_2,
+ int num_cycles_1, int num_cycles_3, int num_cycles_4, int reverse)
{
struct stru1 vv;
char multiplier;
- compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1,
- 0, 1, &vv);
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1, 0, 1, &vv);
multiplier =
- div_roundup(max
- (div_roundup(num_cycles_2, vv.common_time_unit_ps) +
- div_roundup(num_cycles_3, vv.common_time_unit_ps),
- div_roundup(num_cycles_1,
- vv.common_time_unit_ps) +
- div_roundup(num_cycles_4, vv.common_time_unit_ps))
- + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1;
+ div_roundup(max(div_roundup(num_cycles_2, vv.common_time_unit_ps)
+ + div_roundup(num_cycles_3, vv.common_time_unit_ps),
+ div_roundup(num_cycles_1, vv.common_time_unit_ps)
+ + div_roundup(num_cycles_4, vv.common_time_unit_ps))
+ + vv.freq_min_reduced - 1,
+ vv.freq_max_reduced)
+ - 1;
- u32 y =
- (u8) ((vv.freq_max_reduced - vv.freq_min_reduced) +
- vv.freq_max_reduced * multiplier)
- | (vv.
- freqs_reversed << 8) | ((u8) (vv.freq_min_reduced *
- multiplier) << 16) | ((u8) (vv.
- freq_min_reduced
- *
- multiplier)
- << 24);
- u32 x =
- vv.freq3_to_2_remaindera | (vv.freq4_to_2_remainder << 8) | (vv.
- divisor_f3_to_f1
- << 16)
- | (vv.divisor_f4_to_f2 << 20) | (vv.freq_min_reduced << 24);
+ u32 y = (u8)((vv.freq_max_reduced - vv.freq_min_reduced)
+ + vv.freq_max_reduced * multiplier)
+ | (vv.freqs_reversed << 8) | ((u8)(vv.freq_min_reduced * multiplier) << 16)
+ | ((u8)(vv.freq_min_reduced * multiplier) << 24);
+ u32 x = vv.freq3_to_2_remaindera | (vv.freq4_to_2_remainder << 8)
+ | (vv.divisor_f3_to_f1 << 16) | (vv.divisor_f4_to_f2 << 20)
+ | (vv.freq_min_reduced << 24);
if (reverse) {
MCHBAR32(reg) = y;
MCHBAR32(reg + 4) = x;
@@ -3411,134 +3105,107 @@
}
}
-static void
-set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
- int num_cycles_1, int num_cycles_2, int num_cycles_3,
- int num_cycles_4)
+static void set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, int num_cycles_1,
+ int num_cycles_2, int num_cycles_3, int num_cycles_4)
{
struct stru1 ratios1;
struct stru1 ratios2;
- compute_frequence_ratios(info, freq1, freq2, num_cycles_1, num_cycles_2,
- 0, 1, &ratios2);
- compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4,
- 0, 1, &ratios1);
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_1, num_cycles_2, 0, 1,
+ &ratios2);
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1,
+ &ratios1);
printk(RAM_SPEW, "[%x] <= %x\n", reg,
- ratios1.freq4_to_max_remainder | (ratios2.
- freq4_to_max_remainder
- << 8)
- | (ratios1.divisor_f4_to_fmax << 16) | (ratios2.
- divisor_f4_to_fmax
- << 20));
- MCHBAR32(reg) = ratios1.freq4_to_max_remainder |
- (ratios2.freq4_to_max_remainder << 8) |
- (ratios1.divisor_f4_to_fmax << 16) |
- (ratios2.divisor_f4_to_fmax << 20);
+ ratios1.freq4_to_max_remainder | (ratios2.freq4_to_max_remainder << 8)
+ | (ratios1.divisor_f4_to_fmax << 16)
+ | (ratios2.divisor_f4_to_fmax << 20));
+ MCHBAR32(reg) = ratios1.freq4_to_max_remainder | (ratios2.freq4_to_max_remainder << 8)
+ | (ratios1.divisor_f4_to_fmax << 16)
+ | (ratios2.divisor_f4_to_fmax << 20);
}
-static void
-set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
- int num_cycles_2, int num_cycles_1, int round_it, int add_freqs)
+static void set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
+ int num_cycles_2, int num_cycles_1, int round_it, int add_freqs)
{
struct stru1 ratios;
- compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1,
- round_it, add_freqs, &ratios);
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1, round_it,
+ add_freqs, &ratios);
switch (mode) {
case 0:
- MCHBAR32(reg + 4) = ratios.freq_diff_reduced |
- (ratios.freqs_reversed << 8);
- MCHBAR32(reg) = ratios.freq3_to_2_remainder |
- (ratios.freq4_to_max_remainder << 8) |
- (ratios.divisor_f3_to_fmax << 16) |
- (ratios.divisor_f4_to_fmax << 20) |
- (ratios.freq_min_reduced << 24);
+ MCHBAR32(reg + 4) = ratios.freq_diff_reduced | (ratios.freqs_reversed << 8);
+ MCHBAR32(reg) =
+ ratios.freq3_to_2_remainder | (ratios.freq4_to_max_remainder << 8)
+ | (ratios.divisor_f3_to_fmax << 16) | (ratios.divisor_f4_to_fmax << 20)
+ | (ratios.freq_min_reduced << 24);
break;
case 1:
- MCHBAR32(reg) = ratios.freq3_to_2_remainder |
- (ratios.divisor_f3_to_fmax << 16);
+ MCHBAR32(reg) = ratios.freq3_to_2_remainder | (ratios.divisor_f3_to_fmax << 16);
break;
case 2:
- MCHBAR32(reg) = ratios.freq3_to_2_remainder |
- (ratios.freq4_to_max_remainder << 8) |
- (ratios.divisor_f3_to_fmax << 16) |
- (ratios.divisor_f4_to_fmax << 20);
+ MCHBAR32(reg) =
+ ratios.freq3_to_2_remainder | (ratios.freq4_to_max_remainder << 8)
+ | (ratios.divisor_f3_to_fmax << 16) | (ratios.divisor_f4_to_fmax << 20);
break;
case 4:
- MCHBAR32(reg) = (ratios.divisor_f3_to_fmax << 4) |
- (ratios.divisor_f4_to_fmax << 8) |
- (ratios.freqs_reversed << 12) |
- (ratios.freq_min_reduced << 16) |
- (ratios.freq_diff_reduced << 24);
+ MCHBAR32(reg) =
+ (ratios.divisor_f3_to_fmax << 4) | (ratios.divisor_f4_to_fmax << 8)
+ | (ratios.freqs_reversed << 12) | (ratios.freq_min_reduced << 16)
+ | (ratios.freq_diff_reduced << 24);
break;
}
}
static void set_2dxx_series(struct raminfo *info, int s3resume)
{
- set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005,
- 0, 1);
+ set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005, 0, 1);
set_2dx8_reg(info, 0x2d08, 0, 0x78, 0x78, 3273, 5033, 1, 1);
- set_2dx8_reg(info, 0x2d10, 0, 0x78, info->fsb_frequency, 1475, 1131, 0,
+ set_2dx8_reg(info, 0x2d10, 0, 0x78, info->fsb_frequency, 1475, 1131, 0, 1);
+ set_2dx8_reg(info, 0x2d18, 0, 2 * info->fsb_frequency, frequency_11(info), 1231, 1524,
+ 0, 1);
+ set_2dx8_reg(info, 0x2d20, 0, 2 * info->fsb_frequency, frequency_11(info) / 2, 1278,
+ 2008, 0, 1);
+ set_2dx8_reg(info, 0x2d28, 0, info->fsb_frequency, frequency_11(info), 1167, 1539, 0,
1);
- set_2dx8_reg(info, 0x2d18, 0, 2 * info->fsb_frequency,
- frequency_11(info), 1231, 1524, 0, 1);
- set_2dx8_reg(info, 0x2d20, 0, 2 * info->fsb_frequency,
- frequency_11(info) / 2, 1278, 2008, 0, 1);
- set_2dx8_reg(info, 0x2d28, 0, info->fsb_frequency, frequency_11(info),
- 1167, 1539, 0, 1);
- set_2dx8_reg(info, 0x2d30, 0, info->fsb_frequency,
- frequency_11(info) / 2, 1403, 1318, 0, 1);
- set_2dx8_reg(info, 0x2d38, 0, info->fsb_frequency, 0x78, 3460, 5363, 1,
- 1);
- set_2dx8_reg(info, 0x2d40, 0, info->fsb_frequency, 0x3c, 2792, 5178, 1,
- 1);
- set_2dx8_reg(info, 0x2d48, 0, 2 * info->fsb_frequency, 0x78, 2738, 4610,
- 1, 1);
- set_2dx8_reg(info, 0x2d50, 0, info->fsb_frequency, 0x78, 2819, 5932, 1,
- 1);
- set_2dx8_reg(info, 0x6d4, 1, info->fsb_frequency,
- frequency_11(info) / 2, 4000, 0, 0, 0);
- set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency,
- frequency_11(info) / 2, 4000, 4000, 0, 0);
+ set_2dx8_reg(info, 0x2d30, 0, info->fsb_frequency, frequency_11(info) / 2, 1403, 1318,
+ 0, 1);
+ set_2dx8_reg(info, 0x2d38, 0, info->fsb_frequency, 0x78, 3460, 5363, 1, 1);
+ set_2dx8_reg(info, 0x2d40, 0, info->fsb_frequency, 0x3c, 2792, 5178, 1, 1);
+ set_2dx8_reg(info, 0x2d48, 0, 2 * info->fsb_frequency, 0x78, 2738, 4610, 1, 1);
+ set_2dx8_reg(info, 0x2d50, 0, info->fsb_frequency, 0x78, 2819, 5932, 1, 1);
+ set_2dx8_reg(info, 0x6d4, 1, info->fsb_frequency, frequency_11(info) / 2, 4000, 0, 0,
+ 0);
+ set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency, frequency_11(info) / 2, 4000, 4000, 0,
+ 0);
if (s3resume) {
- printk(RAM_SPEW, "[6dc] <= %x\n",
- info->cached_training->reg_6dc);
+ printk(RAM_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc);
MCHBAR32(0x6dc) = info->cached_training->reg_6dc;
} else
set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0,
- info->delay46_ps[0], 0,
- info->delay54_ps[0]);
- set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency,
- frequency_11(info), 2500, 0, 0, 0);
- set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency,
- frequency_11(info) / 2, 3500, 0, 0, 0);
+ info->delay46_ps[0], 0, info->delay54_ps[0]);
+ set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency, frequency_11(info), 2500, 0, 0,
+ 0);
+ set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0,
+ 0, 0);
if (s3resume) {
- printk(RAM_SPEW, "[6e8] <= %x\n",
- info->cached_training->reg_6e8);
+ printk(RAM_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8);
MCHBAR32(0x6e8) = info->cached_training->reg_6e8;
} else
set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0,
- info->delay46_ps[1], 0,
- info->delay54_ps[1]);
+ info->delay46_ps[1], 0, info->delay54_ps[1]);
set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0);
- set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455,
- 470, 0);
+ set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455, 470, 0);
set_2d5x_reg(info, 0x2d68, 0x195, 0x3c, 2707, 5632, 3277, 2207, 0);
- set_2d5x_reg(info, 0x2d70, 0x195, frequency_11(info) / 2, 1276, 758,
- 454, 459, 0);
+ set_2d5x_reg(info, 0x2d70, 0x195, frequency_11(info) / 2, 1276, 758, 454, 459, 0);
set_2d5x_reg(info, 0x2d78, 0x195, 0x78, 1021, 799, 510, 513, 0);
- set_2d5x_reg(info, 0x2d80, info->fsb_frequency, 0xe1, 0, 2862, 2579,
- 2588, 0);
- set_2d5x_reg(info, 0x2d88, info->fsb_frequency, 0xe1, 0, 2690, 2405,
- 2405, 0);
+ set_2d5x_reg(info, 0x2d80, info->fsb_frequency, 0xe1, 0, 2862, 2579, 2588, 0);
+ set_2d5x_reg(info, 0x2d88, info->fsb_frequency, 0xe1, 0, 2690, 2405, 2405, 0);
set_2d5x_reg(info, 0x2da0, 0x78, 0xe1, 0, 2560, 2264, 2251, 0);
- set_2d5x_reg(info, 0x2da8, 0x195, frequency_11(info), 1060, 775, 484,
- 480, 0);
+ set_2d5x_reg(info, 0x2da8, 0x195, frequency_11(info), 1060, 775, 484, 480, 0);
set_2d5x_reg(info, 0x2db0, 0x195, 0x78, 4183, 6023, 2217, 2048, 0);
MCHBAR32(0x2dbc) = ((frequency_11(info) / 2) - 1) | 0xe00000;
MCHBAR32(0x2db8) = ((info->fsb_frequency - 1) << 16) | 0x77;
@@ -3555,13 +3222,14 @@
if (info->revision < 8)
return 256;
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank)
+ {
if (info->populated_ranks[channel][slot][rank])
for (lane = 0; lane < 8 + info->use_ecc; lane++)
ret = max(ret, read_500(info, channel,
- get_timing_register_addr
- (lane, 0, slot,
- rank), 9));
+ get_timing_register_addr(lane, 0, slot,
+ rank),
+ 9));
}
return ret;
}
@@ -3576,23 +3244,18 @@
delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info);
info->training.reg2ca9_bit0 = 0;
- FOR_EACH_CHANNEL(channel) {
- cycletime_ps =
- 900000 / lcm(2 * info->fsb_frequency, frequency_11(info));
- delay_d_ps =
- (halfcycle_ps(info) * get_max_timing(info, channel) >> 6)
- - info->some_delay_3_ps_rounded + 200;
- if (!
- ((info->silicon_revision == 0
- || info->silicon_revision == 1)
- && (info->revision >= 8)))
+ FOR_EACH_CHANNEL(channel)
+ {
+ cycletime_ps = 900000 / lcm(2 * info->fsb_frequency, frequency_11(info));
+ delay_d_ps = (halfcycle_ps(info) * get_max_timing(info, channel) >> 6)
+ - info->some_delay_3_ps_rounded + 200;
+ if (!((info->silicon_revision == 0 || info->silicon_revision == 1)
+ && (info->revision >= 8)))
delay_d_ps += halfcycle_ps(info) * 2;
- delay_d_ps +=
- halfcycle_ps(info) * (!info->revision_flag_1 +
- info->some_delay_2_halfcycles_ceil +
- 2 * info->some_delay_1_cycle_floor +
- info->clock_speed_index +
- 2 * info->cas_latency - 7 + 11);
+ delay_d_ps += halfcycle_ps(info)
+ * (!info->revision_flag_1 + info->some_delay_2_halfcycles_ceil
+ + 2 * info->some_delay_1_cycle_floor + info->clock_speed_index
+ + 2 * info->cas_latency - 7 + 11);
delay_d_ps += info->revision >= 8 ? 2758 : 4428;
MCHBAR32_AND_OR(0x140, 0xfaffffff, 0x2000000);
@@ -3603,22 +3266,19 @@
if (delay_c_ps <= delay_a_ps)
delay_e_ps = 0;
else
- delay_e_ps =
- cycletime_ps * div_roundup(delay_c_ps - delay_a_ps,
- cycletime_ps);
+ delay_e_ps = cycletime_ps
+ * div_roundup(delay_c_ps - delay_a_ps, cycletime_ps);
delay_e_over_cycle_ps = delay_e_ps % (2 * halfcycle_ps(info));
delay_e_cycles = delay_e_ps / (2 * halfcycle_ps(info));
delay_f_cycles =
- div_roundup(2500 - delay_e_over_cycle_ps,
- 2 * halfcycle_ps(info));
+ div_roundup(2500 - delay_e_over_cycle_ps, 2 * halfcycle_ps(info));
if (delay_f_cycles > delay_e_cycles) {
info->delay46_ps[channel] = delay_e_ps;
delay_e_cycles = 0;
} else {
info->delay46_ps[channel] =
- delay_e_over_cycle_ps +
- 2 * halfcycle_ps(info) * delay_f_cycles;
+ delay_e_over_cycle_ps + 2 * halfcycle_ps(info) * delay_f_cycles;
delay_e_cycles -= delay_f_cycles;
}
@@ -3631,28 +3291,25 @@
delay_b_ps = 0;
else
delay_b_ps -= delay_a_ps;
- info->delay54_ps[channel] =
- cycletime_ps * div_roundup(delay_b_ps,
- cycletime_ps) -
- 2 * halfcycle_ps(info) * delay_e_cycles;
+ info->delay54_ps[channel] = cycletime_ps * div_roundup(delay_b_ps, cycletime_ps)
+ - 2 * halfcycle_ps(info) * delay_e_cycles;
if (info->delay54_ps[channel] < 2500)
info->delay54_ps[channel] = 2500;
info->training.reg274265[channel][0] = delay_e_cycles;
- if (delay_d_ps + 7 * halfcycle_ps(info) <=
- 24 * halfcycle_ps(info))
+ if (delay_d_ps + 7 * halfcycle_ps(info) <= 24 * halfcycle_ps(info))
info->training.reg274265[channel][1] = 0;
else
info->training.reg274265[channel][1] =
div_roundup(delay_d_ps + 7 * halfcycle_ps(info),
- 4 * halfcycle_ps(info)) - 6;
+ 4 * halfcycle_ps(info))
+ - 6;
MCHBAR32((channel << 10) + 0x274) =
- info->training.reg274265[channel][1] |
- (info->training.reg274265[channel][0] << 16);
+ info->training.reg274265[channel][1]
+ | (info->training.reg274265[channel][0] << 16);
info->training.reg274265[channel][2] =
- div_roundup(delay_c_ps + 3 * fsbcycle_ps(info),
- 4 * halfcycle_ps(info)) + 1;
- MCHBAR16((channel << 10) + 0x265) =
- info->training.reg274265[channel][2] << 8;
+ div_roundup(delay_c_ps + 3 * fsbcycle_ps(info), 4 * halfcycle_ps(info))
+ + 1;
+ MCHBAR16((channel << 10) + 0x265) = info->training.reg274265[channel][2] << 8;
}
if (info->training.reg2ca9_bit0)
MCHBAR8_OR(0x2ca9, 1);
@@ -3664,12 +3321,13 @@
{
int channel;
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR32((channel << 10) + 0x274) =
- (info->cached_training->reg274265[channel][0] << 16) |
- info->cached_training->reg274265[channel][1];
- MCHBAR16((channel << 10) + 0x265) =
- info->cached_training->reg274265[channel][2] << 8;
+ (info->cached_training->reg274265[channel][0] << 16)
+ | info->cached_training->reg274265[channel][1];
+ MCHBAR16((channel << 10) + 0x265) = info->cached_training->reg274265[channel][2]
+ << 8;
}
if (info->cached_training->reg2ca9_bit0)
MCHBAR8_OR(0x2ca9, 1);
@@ -3688,7 +3346,7 @@
outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
DEFAULT_GPIOBASE | 0x38);
- gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e
+ gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e
}
void chipset_init(const int s3resume)
@@ -3727,15 +3385,15 @@
pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2);
u16 deven;
- deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3
+ deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3
if (deven & 8) {
MCHBAR8(0x2c30) = 0x20;
- pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18
+ pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18
MCHBAR16_OR(0x2c30, 0x200);
MCHBAR16(0x2c32) = 0x434;
MCHBAR32_AND_OR(0x2c44, 0, 0x1053687);
- pci_read_config8(GMA, 0x62); // = 0x2
+ pci_read_config8(GMA, 0x62); // = 0x2
pci_write_config8(GMA, 0x62, 0x2);
read8(DEFAULT_RCBA + 0x2318);
write8(DEFAULT_RCBA + 0x2318, 0x47);
@@ -3787,8 +3445,8 @@
/* before SPD */
timestamp_add_now(101);
- if (!s3resume || 1) { // possible error
- pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
+ if (!s3resume || 1) { // possible error
+ pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
collect_system_info(&info);
@@ -3798,41 +3456,79 @@
memset(&info.populated_ranks, 0, sizeof(info.populated_ranks));
info.use_ecc = 1;
- FOR_EACH_CHANNEL(channel) {
- FOR_EACH_SLOT(slot) {
+ FOR_EACH_CHANNEL(channel)
+ {
+ FOR_EACH_SLOT(slot)
+ {
int v;
- int try;
+ int
+ try
+ ;
int addr;
- const u8 useful_addresses[] = {
- DEVICE_TYPE,
- MODULE_TYPE,
- DENSITY,
- RANKS_AND_DQ,
- MEMORY_BUS_WIDTH,
- TIMEBASE_DIVIDEND,
- TIMEBASE_DIVISOR,
- CYCLETIME,
- CAS_LATENCIES_LSB,
- CAS_LATENCIES_MSB,
- CAS_LATENCY_TIME,
- 0x11, 0x12, 0x13, 0x14, 0x15,
- 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
- 0x1c, 0x1d,
- THERMAL_AND_REFRESH,
- 0x20,
- REFERENCE_RAW_CARD_USED,
- RANK1_ADDRESS_MAPPING,
- 0x75, 0x76, 0x77, 0x78,
- 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e,
- 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84,
- 0x85, 0x86, 0x87, 0x88,
- 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e,
- 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94,
- 0x95
- };
+ const u8 useful_addresses[] = {DEVICE_TYPE,
+ MODULE_TYPE,
+ DENSITY,
+ RANKS_AND_DQ,
+ MEMORY_BUS_WIDTH,
+ TIMEBASE_DIVIDEND,
+ TIMEBASE_DIVISOR,
+ CYCLETIME,
+ CAS_LATENCIES_LSB,
+ CAS_LATENCIES_MSB,
+ CAS_LATENCY_TIME,
+ 0x11,
+ 0x12,
+ 0x13,
+ 0x14,
+ 0x15,
+ 0x16,
+ 0x17,
+ 0x18,
+ 0x19,
+ 0x1a,
+ 0x1b,
+ 0x1c,
+ 0x1d,
+ THERMAL_AND_REFRESH,
+ 0x20,
+ REFERENCE_RAW_CARD_USED,
+ RANK1_ADDRESS_MAPPING,
+ 0x75,
+ 0x76,
+ 0x77,
+ 0x78,
+ 0x79,
+ 0x7a,
+ 0x7b,
+ 0x7c,
+ 0x7d,
+ 0x7e,
+ 0x7f,
+ 0x80,
+ 0x81,
+ 0x82,
+ 0x83,
+ 0x84,
+ 0x85,
+ 0x86,
+ 0x87,
+ 0x88,
+ 0x89,
+ 0x8a,
+ 0x8b,
+ 0x8c,
+ 0x8d,
+ 0x8e,
+ 0x8f,
+ 0x90,
+ 0x91,
+ 0x92,
+ 0x93,
+ 0x94,
+ 0x95};
if (!spd_addrmap[2 * channel + slot])
continue;
- for (try = 0; try < 5; try++) {
+ for (try = 0; try < 5; try ++) {
v = smbus_read_byte(spd_addrmap[2 * channel + slot],
DEVICE_TYPE);
if (v >= 0)
@@ -3840,52 +3536,43 @@
}
if (v < 0)
continue;
- for (addr = 0;
- addr <
- sizeof(useful_addresses) /
- sizeof(useful_addresses[0]); addr++)
- gav(info.
- spd[channel][0][useful_addresses
- [addr]] =
- smbus_read_byte(spd_addrmap[2 * channel + slot],
- useful_addresses
- [addr]));
+ for (addr = 0; addr < sizeof(useful_addresses)
+ / sizeof(useful_addresses[0]);
+ addr++)
+ gav(info.spd[channel][0][useful_addresses[addr]] =
+ smbus_read_byte(
+ spd_addrmap[2 * channel + slot],
+ useful_addresses[addr]));
if (info.spd[channel][0][DEVICE_TYPE] != 11)
die("Only DDR3 is supported");
v = info.spd[channel][0][RANKS_AND_DQ];
info.populated_ranks[channel][0][0] = 1;
- info.populated_ranks[channel][0][1] =
- ((v >> 3) & 7);
+ info.populated_ranks[channel][0][1] = ((v >> 3) & 7);
if (((v >> 3) & 7) > 1)
die("At most 2 ranks are supported");
if ((v & 7) == 0 || (v & 7) > 2)
die("Only x8 and x16 modules are supported");
- if ((info.
- spd[channel][slot][MODULE_TYPE] & 0xF) != 2
- && (info.
- spd[channel][slot][MODULE_TYPE] & 0xF)
- != 3)
+ if ((info.spd[channel][slot][MODULE_TYPE] & 0xF) != 2
+ && (info.spd[channel][slot][MODULE_TYPE] & 0xF) != 3)
die("Registered memory is not supported");
info.is_x16_module[channel][0] = (v & 7) - 1;
info.density[channel][slot] =
- info.spd[channel][slot][DENSITY] & 0xF;
- if (!
- (info.
- spd[channel][slot][MEMORY_BUS_WIDTH] &
- 0x18))
+ info.spd[channel][slot][DENSITY] & 0xF;
+ if (!(info.spd[channel][slot][MEMORY_BUS_WIDTH] & 0x18))
info.use_ecc = 0;
}
}
gav(0x55);
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
int v = 0;
- FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
- v |= info.
- populated_ranks[channel][slot][rank]
- << (2 * slot + rank);
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank)
+ {
+ v |= info.populated_ranks[channel][slot][rank]
+ << (2 * slot + rank);
}
info.populated_ranks_mask[channel] = v;
}
@@ -3917,18 +3604,16 @@
/* Clear bit7. */
- pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
- (reg8 & ~(1 << 7)));
+ pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, (reg8 & ~(1 << 7)));
- printk(BIOS_INFO,
- "Interrupted RAM init, reset required.\n");
+ printk(BIOS_INFO, "Interrupted RAM init, reset required.\n");
system_reset();
}
}
if (!s3resume && x2ca8 == 0)
pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
- pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80);
+ pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80);
compute_derived_timings(&info);
@@ -3942,7 +3627,7 @@
MCHBAR32_OR(0x1890, 0x2000000);
MCHBAR32_OR(0x18b4, 0x8000);
- gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!!
+ gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!!
pci_write_config8(PCI_DEV(0xff, 2, 1), 0x54, 0x12);
gav(MCHBAR16(0x2c10));
@@ -3950,13 +3635,13 @@
gav(MCHBAR16(0x2c10));
MCHBAR16_OR(0x2c12, 0x100);
- gav(MCHBAR8(0x2ca8)); // !!!!
+ gav(MCHBAR8(0x2ca8)); // !!!!
MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080);
- pci_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!!
+ pci_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!!
pci_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0);
- gav(MCHBAR32(0x1c04)); // !!!!
- gav(MCHBAR32(0x1804)); // !!!!
+ gav(MCHBAR32(0x1c04)); // !!!!
+ gav(MCHBAR32(0x1804)); // !!!!
if (x2ca8 == 0) {
MCHBAR8_OR(0x2ca8, 1);
@@ -3976,59 +3661,59 @@
pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x142);
MCHBAR32(0x18d8) = 0x1e0000;
- gav(MCHBAR32(0x18dc)); // !!!!
+ gav(MCHBAR32(0x18dc)); // !!!!
MCHBAR32(0x18dc) = 0x3;
- gav(MCHBAR32(0x18dc)); // !!!!
+ gav(MCHBAR32(0x18dc)); // !!!!
if (x2ca8 == 0) {
- MCHBAR8_OR(0x2ca8, 1); // guess
+ MCHBAR8_OR(0x2ca8, 1); // guess
}
MCHBAR32(0x188c) = 0x20bc09;
pci_write_config32(PCI_DEV(0xff, 2, 1), 0xd0, 0x40b0c09);
MCHBAR32(0x1a10) = 0x4200010e;
MCHBAR32_OR(0x18b8, 0x200);
- gav(MCHBAR32(0x1918)); // !!!!
+ gav(MCHBAR32(0x1918)); // !!!!
MCHBAR32(0x1918) = 0x332;
- gav(MCHBAR32(0x18b8)); // !!!!
+ gav(MCHBAR32(0x18b8)); // !!!!
MCHBAR32(0x18b8) = 0xe00;
- gav(MCHBAR32(0x182c)); // !!!!
+ gav(MCHBAR32(0x182c)); // !!!!
MCHBAR32(0x182c) = 0x10202;
- gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!!
+ gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!!
pci_write_config32(PCI_DEV(0xff, 2, 1), 0x94, 0x10202);
MCHBAR32_AND(0x1a1c, 0x8fffffff);
MCHBAR32_OR(0x1a70, 0x100000);
MCHBAR32_AND(0x18b4, 0xffff7fff);
- gav(MCHBAR32(0x1a68)); // !!!!
+ gav(MCHBAR32(0x1a68)); // !!!!
MCHBAR32(0x1a68) = 0x343800;
- gav(MCHBAR32(0x1e68)); // !!!!
- gav(MCHBAR32(0x1a68)); // !!!!
+ gav(MCHBAR32(0x1e68)); // !!!!
+ gav(MCHBAR32(0x1a68)); // !!!!
if (x2ca8 == 0) {
- MCHBAR8_OR(0x2ca8, 1); // guess
+ MCHBAR8_OR(0x2ca8, 1); // guess
}
- pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!!
+ pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!!
pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000);
- pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
+ pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555);
- pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
- pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!!
- pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180);
- gav(MCHBAR32(0x1af0)); // !!!!
- gav(MCHBAR32(0x1af0)); // !!!!
+ pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
+ pci_read_config32(PCI_DEV(0xff, 0, 0), 0xd0); // !!!!
+ pci_write_config32(PCI_DEV(0xff, 0, 0), 0xd0, 0x180);
+ gav(MCHBAR32(0x1af0)); // !!!!
+ gav(MCHBAR32(0x1af0)); // !!!!
MCHBAR32(0x1af0) = 0x1f020003;
- gav(MCHBAR32(0x1af0)); // !!!!
+ gav(MCHBAR32(0x1af0)); // !!!!
if (x2ca8 == 0) {
- MCHBAR8_OR(0x2ca8, 1); // guess
+ MCHBAR8_OR(0x2ca8, 1); // guess
}
- gav(MCHBAR32(0x1890)); // !!!!
+ gav(MCHBAR32(0x1890)); // !!!!
MCHBAR32(0x1890) = 0x80102;
- gav(MCHBAR32(0x18b4)); // !!!!
+ gav(MCHBAR32(0x18b4)); // !!!!
MCHBAR32(0x18b4) = 0x216000;
MCHBAR32(0x18a4) = 0x22222222;
MCHBAR32(0x18a8) = 0x22222222;
@@ -4046,16 +3731,15 @@
info.cached_training->reg2ca9_bit0);
for (i = 0; i < 2; i++)
for (j = 0; j < 3; j++)
- printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n",
- i, j, info.cached_training->reg274265[i][j]);
+ printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j,
+ info.cached_training->reg274265[i][j]);
} else {
set_274265(&info);
- printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n",
- info.training.reg2ca9_bit0);
+ printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.training.reg2ca9_bit0);
for (i = 0; i < 2; i++)
for (j = 0; j < 3; j++)
- printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n",
- i, j, info.training.reg274265[i][j]);
+ printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j,
+ info.training.reg274265[i][j]);
}
set_2dxx_series(&info, s3resume);
@@ -4069,9 +3753,9 @@
if (deven & 8) {
MCHBAR32_OR(0xff8, 0x1800);
MCHBAR32_AND(0x2cb0, 0x00);
- pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
- pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
- pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
+ pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4c);
+ pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4c);
+ pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4e);
MCHBAR8(0x1150);
MCHBAR8(0x1151);
@@ -4263,25 +3947,25 @@
MCHBAR16(0x1220) = 0x1388;
}
- MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!!
- MCHBAR32(0x1c04); // !!!!
+ MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!!
+ MCHBAR32(0x1c04); // !!!!
MCHBAR32(0x1804) = 0x406080;
MCHBAR8(0x2ca8);
if (x2ca8 == 0) {
MCHBAR8_AND(0x2ca8, ~3);
- MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"?
+ MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"?
MCHBAR32_OR(0x1af0, 0x10);
halt();
}
MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8);
- MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!!
- pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220);
- MCHBAR16(0x2c20); // !!!!
- MCHBAR16(0x2c10); // !!!!
- MCHBAR16(0x2c00); // !!!!
+ MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!!
+ pci_write_config32(PCI_DEV(0xff, 0, 0), 0x60, 0x20220);
+ MCHBAR16(0x2c20); // !!!!
+ MCHBAR16(0x2c10); // !!!!
+ MCHBAR16(0x2c00); // !!!!
MCHBAR16(0x2c00) = 0x8c0;
udelay(1000);
write_1d0(0, 0x33d, 0, 0);
@@ -4289,18 +3973,20 @@
write_500(&info, 1, 0, 0xb61, 0, 0);
MCHBAR32(0x1a30) = 0x0;
MCHBAR32(0x1a34) = 0x0;
- MCHBAR16(0x614) = 0xb5b | (info.populated_ranks[1][0][0] * 0x404) |
- (info.populated_ranks[0][0][0] * 0xa0);
+ MCHBAR16(0x614) = 0xb5b | (info.populated_ranks[1][0][0] * 0x404)
+ | (info.populated_ranks[0][0][0] * 0xa0);
MCHBAR16(0x616) = 0x26a;
MCHBAR32(0x134) = 0x856000;
MCHBAR32(0x160) = 0x5ffffff;
- MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!!
+ MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!!
MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!!
- FOR_EACH_CHANNEL(channel) {
- MCHBAR32(0x260 + (channel << 10)) = 0x30809ff |
- ((info.populated_ranks_mask[channel] & 3) << 20);
+ FOR_EACH_CHANNEL(channel)
+ {
+ MCHBAR32(0x260 + (channel << 10)) =
+ 0x30809ff | ((info.populated_ranks_mask[channel] & 3) << 20);
}
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR16(0x31c + (channel << 10)) = 0x101;
MCHBAR16(0x360 + (channel << 10)) = 0x909;
MCHBAR16(0x3a4 + (channel << 10)) = 0x101;
@@ -4318,17 +4004,17 @@
write_1d0(0x4, 0x151, 4, 1);
write_1d0(0, 0x142, 3, 1);
- rdmsr(0x1ac); // !!!!
+ rdmsr(0x1ac); // !!!!
write_500(&info, 1, 1, 0x6b3, 4, 1);
write_500(&info, 1, 1, 0x6cf, 4, 1);
rmw_1d0(0x21c, 0x38, 0, 6, 1);
- write_1d0(((!info.populated_ranks[1][0][0]) << 1) | ((!info.
- populated_ranks[0]
- [0][0]) << 0),
+ write_1d0(((!info.populated_ranks[1][0][0]) << 1)
+ | ((!info.populated_ranks[0][0][0]) << 0),
0x1d1, 3, 1);
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR16(0x38e + (channel << 10)) = 0x5f5f;
MCHBAR16(0x3d2 + (channel << 10)) = 0x5f5f;
}
@@ -4344,11 +4030,13 @@
write_1d0(0x0, 0xeb, 3, 1);
write_1d0(0x0, 0xf3, 6, 1);
- FOR_EACH_CHANNEL(channel) {
- FOR_EACH_LANE_WITH_ECC(lane) {
+ FOR_EACH_CHANNEL(channel)
+ {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
u16 addr = 0x125 + get_lane_offset(0, 0, lane);
u8 a;
- a = read_500(&info, channel, addr, 6); // = 0x20040080 //!!!!
+ a = read_500(&info, channel, addr, 6); // = 0x20040080 //!!!!
write_500(&info, channel, a, addr, 6, 1);
}
}
@@ -4358,8 +4046,7 @@
if (s3resume) {
if (info.cached_training == NULL) {
u32 reg32;
- printk(BIOS_ERR,
- "Couldn't find training data. Rebooting\n");
+ printk(BIOS_ERR, "Couldn't find training data. Rebooting\n");
reg32 = inl(DEFAULT_PMBASE + 0x04);
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
full_reset();
@@ -4367,19 +4054,16 @@
int tm;
info.training = *info.cached_training;
for (tm = 0; tm < 4; tm++) {
- FOR_ALL_RANKS(channel, slot, rank) {
- FOR_EACH_LANE_WITH_ECC(lane) {
- write_500(&info,
- channel,
- info.training.
- lane_timings
- [tm][channel]
- [slot][rank]
- [lane],
- get_timing_register_addr
- (lane, tm,
- slot, rank),
- 9, 0);
+ FOR_ALL_RANKS(channel, slot, rank)
+ {
+ FOR_EACH_LANE_WITH_ECC(lane)
+ {
+ write_500(
+ &info, channel,
+ info.training.lane_timings[tm][channel][slot]
+ [rank][lane],
+ get_timing_register_addr(lane, tm, slot, rank),
+ 9, 0);
}
}
}
@@ -4387,10 +4071,10 @@
write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1);
}
- MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!!
+ MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!!
MCHBAR32(0x1f0) = 0x1d000200;
- MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!!
- MCHBAR8(0x1f0); // !!!!
+ MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!!
+ MCHBAR8(0x1f0); // !!!!
program_board_delay(&info);
@@ -4398,29 +4082,29 @@
MCHBAR8(0x5ff) = 0x80;
MCHBAR8(0x5f4) = 0x1;
- MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ?
+ MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ?
while (MCHBAR32(0x130) & 1)
;
- gav(read_1d0(0x14b, 7)); // = 0x81023100
+ gav(read_1d0(0x14b, 7)); // = 0x81023100
write_1d0(0x30, 0x14b, 7, 1);
- read_1d0(0xd6, 6); // = 0xfa008080 // !!!!
+ read_1d0(0xd6, 6); // = 0xfa008080 // !!!!
write_1d0(7, 0xd6, 6, 1);
- read_1d0(0x328, 6); // = 0xfa018080 // !!!!
+ read_1d0(0x328, 6); // = 0xfa018080 // !!!!
write_1d0(7, 0x328, 6, 1);
- FOR_EACH_CHANNEL(channel) {
- set_4cf(&info, channel,
- info.populated_ranks[channel][0][0] ? 8 : 0);
+ FOR_EACH_CHANNEL(channel)
+ {
+ set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 8 : 0);
}
- read_1d0(0x116, 4); // = 0x4040432 // !!!!
+ read_1d0(0x116, 4); // = 0x4040432 // !!!!
write_1d0(2, 0x116, 4, 1);
- read_1d0(0xae, 6); // = 0xe8088080 // !!!!
+ read_1d0(0xae, 6); // = 0xe8088080 // !!!!
write_1d0(0, 0xae, 6, 1);
- read_1d0(0x300, 4); // = 0x48088080 // !!!!
+ read_1d0(0x300, 4); // = 0x48088080 // !!!!
write_1d0(0, 0x300, 6, 1);
- MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!!
- MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!!
+ MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!!
+ MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!!
MCHBAR32_AND(0x140, ~0x07000000);
MCHBAR32_AND(0x138, ~0x07000000);
MCHBAR32(0x130) = 0x31111301;
@@ -4431,63 +4115,58 @@
{
u32 t;
u8 val_a1;
- val_a1 = read_1d0(0xa1, 6); // = 0x1cf4040 // !!!!
- t = read_1d0(0x2f3, 6); // = 0x10a4040 // !!!!
- rmw_1d0(0x320, 0x07,
- (t & 4) | ((t & 8) >> 2) | ((t & 0x10) >> 4), 6, 1);
- rmw_1d0(0x14b, 0x78,
- ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 &
- 4), 7,
- 1);
- rmw_1d0(0xce, 0x38,
- ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 &
- 4), 6,
- 1);
+ val_a1 = read_1d0(0xa1, 6); // = 0x1cf4040 // !!!!
+ t = read_1d0(0x2f3, 6); // = 0x10a4040 // !!!!
+ rmw_1d0(0x320, 0x07, (t & 4) | ((t & 8) >> 2) | ((t & 0x10) >> 4), 6, 1);
+ rmw_1d0(0x14b, 0x78, ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & 4),
+ 7, 1);
+ rmw_1d0(0xce, 0x38, ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & 4),
+ 6, 1);
}
- FOR_EACH_CHANNEL(channel) {
- set_4cf(&info, channel,
- info.populated_ranks[channel][0][0] ? 9 : 1);
+ FOR_EACH_CHANNEL(channel)
+ {
+ set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 9 : 1);
}
- rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!!
- MCHBAR32(0x144); // !!!!
+ rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!!
+ MCHBAR32(0x144); // !!!!
write_1d0(2, 0xae, 6, 1);
write_1d0(2, 0x300, 6, 1);
write_1d0(2, 0x121, 3, 1);
- read_1d0(0xd6, 6); // = 0xfa00c0c7 // !!!!
+ read_1d0(0xd6, 6); // = 0xfa00c0c7 // !!!!
write_1d0(4, 0xd6, 6, 1);
- read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!!
+ read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!!
write_1d0(4, 0x328, 6, 1);
- FOR_EACH_CHANNEL(channel) {
- set_4cf(&info, channel,
- info.populated_ranks[channel][0][0] ? 9 : 0);
+ FOR_EACH_CHANNEL(channel)
+ {
+ set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 9 : 0);
}
- MCHBAR32(0x130) = 0x11111301 | (info.populated_ranks[1][0][0] << 30) |
- (info.populated_ranks[0][0][0] << 29);
+ MCHBAR32(0x130) = 0x11111301 | (info.populated_ranks[1][0][0] << 30)
+ | (info.populated_ranks[0][0][0] << 29);
while (MCHBAR8(0x130) & 1)
;
- read_1d0(0xa1, 6); // = 0x1cf4054 // !!!!
- read_1d0(0x2f3, 6); // = 0x10a4054 // !!!!
- read_1d0(0x21c, 6); // = 0xafa00c0 // !!!!
+ read_1d0(0xa1, 6); // = 0x1cf4054 // !!!!
+ read_1d0(0x2f3, 6); // = 0x10a4054 // !!!!
+ read_1d0(0x21c, 6); // = 0xafa00c0 // !!!!
write_1d0(0, 0x21c, 6, 1);
- read_1d0(0x14b, 7); // = 0x810231b0 // !!!!
+ read_1d0(0x14b, 7); // = 0x810231b0 // !!!!
write_1d0(0x35, 0x14b, 7, 1);
- FOR_EACH_CHANNEL(channel) {
- set_4cf(&info, channel,
- info.populated_ranks[channel][0][0] ? 0xb : 0x2);
+ FOR_EACH_CHANNEL(channel)
+ {
+ set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 0xb : 0x2);
}
set_334(1);
MCHBAR8(0x1e8) = 0x4;
- FOR_EACH_CHANNEL(channel) {
- write_500(&info, channel,
- 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2,
+ FOR_EACH_CHANNEL(channel)
+ {
+ write_500(&info, channel, 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2,
1);
write_500(&info, channel, 0x3, 0x69b, 2, 1);
}
@@ -4506,42 +4185,45 @@
MCHBAR8(0x271) = 0x2;
MCHBAR8(0x671) = 0x2;
MCHBAR8(0x1e8) = 0x4;
- FOR_EACH_CHANNEL(channel) {
- MCHBAR32(0x294 + (channel << 10)) =
- (info.populated_ranks_mask[channel] & 3) << 16;
+ FOR_EACH_CHANNEL(channel)
+ {
+ MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3)
+ << 16;
}
MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000);
MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000);
- FOR_EACH_CHANNEL(channel) {
- MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 |
- ((info.populated_ranks_mask[channel] & 3) << 20));
+ FOR_EACH_CHANNEL(channel)
+ {
+ MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000,
+ 0x8000000 | ((info.populated_ranks_mask[channel] & 3) << 20));
}
if (!s3resume)
jedec_init(&info);
int totalrank = 0;
- FOR_ALL_POPULATED_RANKS(&info, channel, slot, rank) {
- jedec_read(&info, channel, slot, rank,
- totalrank, 0xa, 0x400);
+ FOR_ALL_POPULATED_RANKS(&info, channel, slot, rank)
+ {
+ jedec_read(&info, channel, slot, rank, totalrank, 0xa, 0x400);
totalrank++;
}
MCHBAR8(0x12c) = 0x9f;
- MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!!
- MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!!
+ MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!!
+ MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!!
if (!s3resume) {
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR32(0x294 + (channel << 10)) =
(info.populated_ranks_mask[channel] & 3) << 16;
MCHBAR16(0x298 + (channel << 10)) =
- info.populated_ranks[channel][0][0] |
- (info.populated_ranks[channel][0][1] << 5);
+ info.populated_ranks[channel][0][0]
+ | (info.populated_ranks[channel][0][1] << 5);
MCHBAR32(0x29c + (channel << 10)) = 0x77a;
}
- MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
+ MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
{
u8 a, b;
@@ -4555,18 +4237,15 @@
write_1d0(7, 0x1c0, 3, 1);
write_1d0(4, 0x1c6, 4, 1);
write_1d0(4, 0x1cc, 4, 1);
- read_1d0(0x151, 4); // = 0x408c6d74 // !!!!
+ read_1d0(0x151, 4); // = 0x408c6d74 // !!!!
write_1d0(4, 0x151, 4, 1);
MCHBAR32(0x584) = 0xfffff;
MCHBAR32(0x984) = 0xfffff;
- FOR_ALL_RANKS(channel, slot, rank) {
- if (info.
- populated_ranks[channel][slot]
- [rank])
- config_rank(&info, s3resume,
- channel, slot,
- rank);
+ FOR_ALL_RANKS(channel, slot, rank)
+ {
+ if (info.populated_ranks[channel][slot][rank])
+ config_rank(&info, s3resume, channel, slot, rank);
}
MCHBAR8(0x243) = 0x1;
@@ -4581,15 +4260,16 @@
/* end */
if (s3resume) {
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR32(0x294 + (channel << 10)) =
(info.populated_ranks_mask[channel] & 3) << 16;
MCHBAR16(0x298 + (channel << 10)) =
- info.populated_ranks[channel][0][0] |
- (info.populated_ranks[channel][0][1] << 5);
+ info.populated_ranks[channel][0][0]
+ | (info.populated_ranks[channel][0][1] << 5);
MCHBAR32(0x29c + (channel << 10)) = 0x77a;
}
- MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
+ MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
}
MCHBAR32_AND(0xfa4, ~0x01000002);
@@ -4659,11 +4339,12 @@
eax = info.fsb_frequency / 9;
MCHBAR32_AND_OR(0xfcc, 0xfffc0000,
- (eax * 0x280) | (eax * 0x5000) | eax | 0x40000);
+ (eax * 0x280) | (eax * 0x5000) | eax | 0x40000);
MCHBAR32(0x20) = 0x33001;
}
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR32_AND(0x220 + (channel << 10), ~0x7770);
if (info.max_slots_used_in_channel == 1)
MCHBAR16_OR(0x237 + (channel << 10), 0x0201);
@@ -4672,8 +4353,8 @@
MCHBAR8_OR(0x241 + (channel << 10), 1);
- if (info.clock_speed_index <= 1 && (info.silicon_revision == 2
- || info.silicon_revision == 3))
+ if (info.clock_speed_index <= 1
+ && (info.silicon_revision == 2 || info.silicon_revision == 3))
MCHBAR32_OR(0x248 + (channel << 10), 0x00102000);
else
MCHBAR32_AND(0x248 + (channel << 10), ~0x00102000);
@@ -4690,19 +4371,20 @@
MCHBAR32(0x210) = (al << 16) | 0x20;
}
- FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_CHANNEL(channel)
+ {
MCHBAR32(0x288 + (channel << 10)) = 0x70605040;
MCHBAR32(0x28c + (channel << 10)) = 0xfffec080;
- MCHBAR32(0x290 + (channel << 10)) = 0x282091c |
- ((info.max_slots_used_in_channel - 1) << 0x16);
+ MCHBAR32(0x290 + (channel << 10)) =
+ 0x282091c | ((info.max_slots_used_in_channel - 1) << 0x16);
}
u32 reg1c;
- pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
- pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
- MCHBAR8(0xe08); // = 0x0
- pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
+ pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+ reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
+ pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+ write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
+ MCHBAR8(0xe08); // = 0x0
+ pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
MCHBAR8_OR(0x1210, 2);
MCHBAR32(0x1200) = 0x8800440;
MCHBAR32(0x1204) = 0x53ff0453;
@@ -4736,7 +4418,7 @@
u8 bl, ebpb;
u16 reg_1020;
- reg_1020 = MCHBAR32(0x1020); // = 0x6c733c // OK
+ reg_1020 = MCHBAR32(0x1020); // = 0x6c733c // OK
MCHBAR8(0x1070) = 0x1;
MCHBAR32(0x1000) = 0x100;
@@ -4773,7 +4455,7 @@
MCHBAR32_OR(0x11b4, 0x4000);
MCHBAR16_OR(0x1190, 0x4000);
- ax = MCHBAR16(0x1190) & 0xf00; // = 0x480a // OK
+ ax = MCHBAR16(0x1190) & 0xf00; // = 0x480a // OK
MCHBAR16(0x1170) = ax | (MCHBAR16(0x1170) & 0x107f) | 0x4080;
MCHBAR16_OR(0x1170, 0x1000);
@@ -4786,7 +4468,7 @@
}
pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
- pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80);
+ pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80);
udelay(10000);
MCHBAR16(0x2ca8) = 0x8;
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