Frans Hendriks has uploaded this change for review.

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src/soc/intel/braswell/acpi/lpss.asl: Remove disabled SPI1 and PWM devices

ACPI code for these devices is enabled, but devices are disabled on the platform.
Remove these devices when disabled.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I97aeb725ee5fb162b958e4f83f73814c55a6066b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
---
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/acpi/lpss.asl
2 files changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29374/1

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 6e3adcd..1f44e78 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -127,6 +127,13 @@
 	string
 	default "soc/intel/braswell/bootblock/timestamp.inc"
 
+config INCLUDE_SPI1_AND_PWM
+	bool "Include ASL code for SPI1 and PWM devices"
+	default y
+	help
+		Enable this if the SPI1 and PWM interfaces are supported
+		This requires an FSP update.
+
 config ENABLE_LPE_DEVICES
 	bool "Include ASL code for LPE devices"
 	default y
diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl
index 4cc93cc..5e71101 100644
--- a/src/soc/intel/braswell/acpi/lpss.asl
+++ b/src/soc/intel/braswell/acpi/lpss.asl
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -522,6 +523,11 @@
 	}
 }
 
+//
+// Remove the devices that can't be enabled from ASL. This will keep Linux from trying to
+// use them even tough they are disabled.
+//
+#if IS_ENABLED(CONFIG_INCLUDE_SPI1_AND_PWM)
 Device (SPI1)
 {
 	Name (_HID, "8086228E")
@@ -630,6 +636,7 @@
 		}
 	}
 }
+#endif
 
 Device (UAR1)
 {

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