Patrick Georgi submitted this change.
mb/asus/p8z77-series: Add P8Z77-V as a variant of P8Z77 series
Mainboard information can be found in the included documentation.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
A Documentation/mainboard/asus/p8z77-v.jpg
A Documentation/mainboard/asus/p8z77-v.md
A Documentation/mainboard/asus/wifigo_v1.md
A Documentation/mainboard/asus/wifigo_v1_board.jpg
A Documentation/mainboard/asus/wifigo_v1_connector.jpg
M Documentation/mainboard/index.md
M src/mainboard/asus/p8z77-series/Kconfig
M src/mainboard/asus/p8z77-series/Kconfig.name
A src/mainboard/asus/p8z77-series/variants/p8z77-v/board_info.txt
A src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.default
A src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.layout
A src/mainboard/asus/p8z77-series/variants/p8z77-v/data.vbt
A src/mainboard/asus/p8z77-series/variants/p8z77-v/early_init.c
A src/mainboard/asus/p8z77-series/variants/p8z77-v/gma-mainboard.ads
A src/mainboard/asus/p8z77-series/variants/p8z77-v/gpio.c
A src/mainboard/asus/p8z77-series/variants/p8z77-v/hda_verb.c
A src/mainboard/asus/p8z77-series/variants/p8z77-v/overridetree.cb
17 files changed, 630 insertions(+), 0 deletions(-)
diff --git a/Documentation/mainboard/asus/p8z77-v.jpg b/Documentation/mainboard/asus/p8z77-v.jpg
new file mode 100644
index 0000000..84acab7
--- /dev/null
+++ b/Documentation/mainboard/asus/p8z77-v.jpg
Binary files differ
diff --git a/Documentation/mainboard/asus/p8z77-v.md b/Documentation/mainboard/asus/p8z77-v.md
new file mode 100644
index 0000000..dba02b9
--- /dev/null
+++ b/Documentation/mainboard/asus/p8z77-v.md
@@ -0,0 +1,112 @@
+# ASUS P8Z77-V
+
+This page describes how to run coreboot on the [ASUS P8Z77-V].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type | Value |
++=====================+================+
+| Socketed flash | yes |
++---------------------+----------------+
+| Model | W25Q64FVA1Q |
++---------------------+----------------+
+| Size | 8 MiB |
++---------------------+----------------+
+| Package | DIP-8 |
++---------------------+----------------+
+| Write protection | yes |
++---------------------+----------------+
+| Dual BIOS feature | no |
++---------------------+----------------+
+| Internal flashing | no |
++---------------------+----------------+
+```
+
+The flash IC is located between the black and white PCI Express x16 slots (circled):
+
+
+### How to flash
+
+The main SPI flash cannot be written because the vendor firmware disables BIOSWE
+and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
+programmer is required. You must flash standalone, flashing in-circuit doesn't
+work. The flash chip is socketed, so it's easy to remove and reflash.
+
+## Working
+
+- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.28
+- Integrated Ethernet NIC
+- S3 Suspend to RAM
+- USB2 on rear and front panel connectors
+- USB3 (Z77's and ASMedia's works)
+- Integrated SATA of Z77
+- Integrated SATA of ASM1061 (works under GNU/Linux but not under SeaBIOS)
+- CPU Temp sensors (tested PSensor on GNU/Linux)
+- TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
+- Native raminit
+- Integrated graphics with libgfxinit (VGA/DVI-D/HDMI tested and working)
+- PCIe in PCIe-16x/8x slots (tested using an S3 Matrix GPU)
+- Debug output from serial port
+- Atheros AR9485 half-height mini PCIe WNIC adapted with Wi-Fi Go! Adapter
+- Default PCIe config (PCIEX_16_3 as 1x, PCIe Port 4 to ASM1061 SATA, see below
+ for other potential options)
+
+## Untested
+
+- EHCI debugging
+- S/PDIF audio
+- PS/2 mouse
+
+## Not working
+
+- PCIEX_1_2 (expected under default PCIe config)
+- Other PCIe configs (see below)
+
+## PCIe config
+On Asus vendor firmware, other than the default config already supported here,
+there remain another two configs: "PCIEX_16_3 as x4, with PCIEX_1_1, PCIEX_1_2
+and onboard ASM1061 disabled" and "PCIEX_16_3 as x1, but PCIe Port 4 to PCIEX_1_2,
+with onboard ASM1061 disabled".
+
+Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, but
+also needs to configure GPIOs in the Super I/O chip different than the default
+config in this board's override tree.
+
+Configuring PCIe Port 4 to PCIEX_1_2 needs to configure GPIOs in the Super I/O
+chip differently than the default config.
+
+I have tried a lot, but sadly I am unable to produce the same result as the vendor
+firmware.
+
+## Asus Wi-Fi Go!
+Asus Wi-Fi Go! has several versions. P8Z77-V has the earliest version.
+See [Asus Wi-Fi Go! v1].
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge | bd82x6x |
++------------------+--------------------------------------------------+
+| CPU | model_206ax |
++------------------+--------------------------------------------------+
+| Super I/O | Nuvoton NCT6779D |
++------------------+--------------------------------------------------+
+| EC | None |
++------------------+--------------------------------------------------+
+| Coprocessor | Intel Management Engine |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q64FVA1Q]
+
+[ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
+[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[Asus Wi-Fi Go! v1]: ./wifigo_v1.md
diff --git a/Documentation/mainboard/asus/wifigo_v1.md b/Documentation/mainboard/asus/wifigo_v1.md
new file mode 100644
index 0000000..d5ad327
--- /dev/null
+++ b/Documentation/mainboard/asus/wifigo_v1.md
@@ -0,0 +1,40 @@
+# Asus Wi-Fi Go! v1
+
+In this version, a standard half-length mPCIe card is mounted on the Asus Wi-Fi
+Go! daughter board, and the daughter board is connected to the motherboard
+through a proprietary 16-1 pin connector.
+
+
+I managed to grope the most pinout of the proprietary connector.
+See [Mini PCIe pinout] for more info.
+
+```eval_rst
++------------+----------+-----------+------------+----------+-----------+
+| WIFIGO Pin | Usage | mPCIe pin | WIFIGO Pin | Usage | mPCIe pin |
++============+==========+===========+============+==========+===========+
+| 1 | 3.3v | (many) | 2 | REFCLK- | 11 |
++------------+----------+-----------+------------+----------+-----------+
+| 3 | GND | (many) | 4 | REFCLK+ | 13 |
++------------+----------+-----------+------------+----------+-----------+
+| 5 | WAKE# | 1 | 6 | PERn0 | 23 |
++------------+----------+-----------+------------+----------+-----------+
+| 7 | (absent) | | 8 | PERp0 | 25 |
++------------+----------+-----------+------------+----------+-----------+
+| 9 | GND | | 10 | PETn0 | 31 |
++------------+----------+-----------+------------+----------+-----------+
+| 11 | PERST# | 20 | 12 | PETp0 | 33 |
++------------+----------+-----------+------------+----------+-----------+
+| 13 | GND | | 14 | (USBD-?) | (36?) |
++------------+----------+-----------+------------+----------+-----------+
+| 15 | 3.3v | | 16 | (USBD+?) | (38?) |
++------------+----------+-----------+------------+----------+-----------+
+```
+
+There are two kinds of daughter boards using this connector. One among them has
+one MMCX antenna connector, the other has two antenna connectors and USB lane
+wired (this kind may be called BT Go!). I can only obtain the former, so I
+cannot confirm the exact way the USB data lane gets wired.
+
+
+## Extra resources
+[Mini PCIe pinout]: https://pinoutguide.com/Slots/mini_pcie_pinout.shtml
diff --git a/Documentation/mainboard/asus/wifigo_v1_board.jpg b/Documentation/mainboard/asus/wifigo_v1_board.jpg
new file mode 100644
index 0000000..f7d97ab
--- /dev/null
+++ b/Documentation/mainboard/asus/wifigo_v1_board.jpg
Binary files differ
diff --git a/Documentation/mainboard/asus/wifigo_v1_connector.jpg b/Documentation/mainboard/asus/wifigo_v1_connector.jpg
new file mode 100644
index 0000000..cd84cba
--- /dev/null
+++ b/Documentation/mainboard/asus/wifigo_v1_connector.jpg
Binary files differ
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index a08cc43..fae5a53 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -22,6 +22,7 @@
- [P8H61-M LX](asus/p8h61-m_lx.md)
- [P8H61-M Pro](asus/p8h61-m_pro.md)
- [P8Z77-M Pro](asus/p8z77-m_pro.md)
+- [P8Z77-V](asus/p8z77-v.md)
## Cavium
diff --git a/src/mainboard/asus/p8z77-series/Kconfig b/src/mainboard/asus/p8z77-series/Kconfig
index 0b28a7e..da0814a 100644
--- a/src/mainboard/asus/p8z77-series/Kconfig
+++ b/src/mainboard/asus/p8z77-series/Kconfig
@@ -23,11 +23,13 @@
string
default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO
default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2
+ default "p8z77-v" if BOARD_ASUS_P8Z77_V
config MAINBOARD_PART_NUMBER
string
default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO
default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
+ default "P8Z77-V" if BOARD_ASUS_P8Z77_V
config OVERRIDE_DEVICETREE
string
diff --git a/src/mainboard/asus/p8z77-series/Kconfig.name b/src/mainboard/asus/p8z77-series/Kconfig.name
index 49ed7e1..a61b82d 100644
--- a/src/mainboard/asus/p8z77-series/Kconfig.name
+++ b/src/mainboard/asus/p8z77-series/Kconfig.name
@@ -13,3 +13,13 @@
select REALTEK_8168_RESET
select SUPERIO_NUVOTON_NCT6779D
select USE_NATIVE_RAMINIT
+
+config BOARD_ASUS_P8Z77_V
+ bool "P8Z77-V"
+ select BOARD_ASUS_P8Z77_SERIES
+ select BOARD_ROMSIZE_KB_8192
+ select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SUPERIO_NUVOTON_NCT6779D
+ select USE_NATIVE_RAMINIT
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/board_info.txt b/src/mainboard/asus/p8z77-series/variants/p8z77-v/board_info.txt
new file mode 100644
index 0000000..3f875f9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.default b/src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.default
new file mode 100644
index 0000000..c7aa620
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.layout b/src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.layout
new file mode 100644
index 0000000..0f9de5e
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/cmos.layout
@@ -0,0 +1,86 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 2 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 3 debug_level
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+
+409 2 e 4 power_on_after_fail
+411 2 e 5 sata_mode
+
+# coreboot config options: northbridge
+416 5 e 6 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+
+# boot_option
+2 0 Fallback
+2 1 Normal
+
+# debug_level
+3 0 Emergency
+3 1 Alert
+3 2 Critical
+3 3 Error
+3 4 Warning
+3 5 Notice
+3 6 Info
+3 7 Debug
+3 8 Spew
+
+# power_on_after_fail
+4 0 Disable
+4 1 Enable
+4 2 Keep
+
+# sata_mode
+5 0 AHCI
+5 1 Compatible
+5 2 Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6 0 32M
+6 1 64M
+6 2 96M
+6 3 128M
+6 4 160M
+6 5 192M
+6 6 224M
+6 7 256M
+6 8 288M
+6 9 320M
+6 10 352M
+6 11 384M
+6 12 416M
+6 13 448M
+6 14 480M
+6 15 512M
+6 16 1024M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/data.vbt b/src/mainboard/asus/p8z77-series/variants/p8z77-v/data.vbt
new file mode 100644
index 0000000..37fa165
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8z77-series/variants/p8z77-v/early_init.c
new file mode 100644
index 0000000..42b4ebc
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/early_init.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 2, 0 },
+ { 1, 2, 0 },
+ { 1, 2, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 2, 2 },
+ { 1, 2, 3 },
+ { 1, 2, 3 },
+ { 1, 2, 4 },
+ { 1, 0, 4 },
+ { 1, 2, 6 },
+ { 1, 2, 5 },
+ { 1, 2, 5 },
+ { 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+ /* Select SIO pin states */
+ pnp_write_config(GLOBAL_DEV, 0x1a, 0x00);
+ pnp_write_config(GLOBAL_DEV, 0x2a, 0x40);
+ pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+
+ /* Power RAM in S3 */
+ pnp_set_logical_device(ACPI_DEV);
+ pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+ nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+ /* Enable UART */
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/gma-mainboard.ads b/src/mainboard/asus/p8z77-series/variants/p8z77-v/gma-mainboard.ads
new file mode 100644
index 0000000..e6b0407
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/gpio.c b/src/mainboard/asus/p8z77-series/variants/p8z77-v/gpio.c
new file mode 100644
index 0000000..5d5e4e7
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/gpio.c
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio48 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/hda_verb.c b/src/mainboard/asus/p8z77-series/variants/p8z77-v/hda_verb.c
new file mode 100644
index 0000000..e431593
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */
+ 0x104384fb, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x104384fb),
+ AZALIA_PIN_CFG(0, 0x11, 0x99430140),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+ AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+ AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01456130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8z77-series/variants/p8z77-v/overridetree.cb
new file mode 100644
index 0000000..77484c7
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v/overridetree.cb
@@ -0,0 +1,72 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1043 0x84ca inherit
+ device pci 01.1 on end # PCIEX_16_2
+ chip southbridge/intel/bd82x6x
+ register "gen1_dec" = "0x000c0291"
+
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x1 or x4)
+ device pci 1c.1 on end # PCIe Port 2 PCIEX_1_1
+ device pci 1c.3 on end # PCIe Port 4 ASM1061 SATA or PCIEX_1_2
+ device pci 1c.4 on end # PCIe Port 5 ASM1083 PCI Bridge
+ device pci 1c.6 on end # PCIe Port 7 Wi-Fi Go!
+ device pci 1c.7 on end # PCIe Port 8 ASM1042 USB3
+
+ device pci 1f.0 on # LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # PS2 KBC
+ io 0x60 = 0x0060 # KBC1 base
+ io 0x62 = 0x0064 # KBC2 base
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
+
+ # KBC 12Mhz/A20 speed/sw KBRST
+ drq 0xf0 = 0x82
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIOs 6-8
+ device pnp 2e.8 off end # WDT1 GPIO 0-1
+ device pnp 2e.108 on end # GPIO0-1
+ device pnp 2e.109 on end # GPIO1
+ device pnp 2e.209 on # GPIO2
+ drq 0xe0 = 0xdf
+ end
+ device pnp 2e.309 on end # GPIO3
+ device pnp 2e.509 on # GPIO5
+ drq 0xf4 = 0xfc
+ end
+ device pnp 2e.a on # ACPI
+ drq 0xe3 = 0x04 # Thermal shutdown event issued
+ drq 0xe7 = 0x11 # Enable 3VSBS to power RAM on S3
+ drq 0xf2 = 0x5d # Enable PME
+ end
+ device pnp 2e.b on # H/W Monitor, FP LED
+ io 0x60 = 0x290
+ io 0x62 = 0
+ irq 0x70 = 0
+ end
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f on # Push-pull/Open-drain
+ drq 0xe4 = 0xfc # GP5 PP
+ drq 0xe6 = 0x7f # GP7 PP
+ end
+ device pnp 2e.14 off end # Port 80 UART
+ device pnp 2e.16 off end # Deep sleep
+ end
+ chip drivers/pc80/tpm
+ device pnp c31.0 on end # TPM
+ end
+ end
+ end
+ end
+end
To view, visit change 54338. To unsubscribe, or for help writing mail filters, visit settings.