1 comment:
File src/northbridge/intel/ironlake/northbridge.c:
Patch Set #2, Line 137: it uncacheable, though, for easier MTRR allocation. */
Another thing that would work is to mention in the commit message that this gap is extraneous, and s […]
I think we might be talking past each other. This is not a workaround.
It's a fix for the code here. One always has to expect alignment gaps.
So there is nothing unexpected.
Even with the 64MiB down alignment removed, we'd still have to align TSEG
to its size (remember SMRR). With 8MiB TSEG and the 4MiB GTT above it,
there is still a 4MiB gap.
It worked with the old allocator because that one chooses one contiguous
region to allocate everything. The new one simply puts resources where
they fit, therefore relies on accurate reservations.
To view, visit change 45325. To unsubscribe, or for help writing mail filters, visit settings.