Patrick Georgi submitted this change.

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Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flag

Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.

Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 57f36ab..637afab 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -19,6 +19,9 @@
register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1"

+ # CNVi BT enable/disable
+ register "CnviBtCore" = "true"
+
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth
@@ -213,7 +216,6 @@
device pci 0e.0 off end # VMD 0x9A0B

# From PCH EDS(576591)
- device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
device pci 10.6 off end # THC0 0xA0D0
device pci 10.7 off end # THC1 0xA0D1
device pci 12.0 on # SensorHUB 0xA0FC
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 70833ee..83b924e 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -19,6 +19,9 @@
register "SaGv" = "SaGv_Disabled"
register "SmbusEnable" = "1"

+ # CNVi BT enable/disable
+ register "CnviBtCore" = "true"
+
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1
@@ -217,7 +220,6 @@
device pci 0e.0 off end # VMD 0x9A0B

# From PCH EDS(576591)
- device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
device pci 10.6 off end # THC0 0xA0D0
device pci 10.7 off end # THC1 0xA0D1
device pci 12.0 on # SensorHUB 0xA0FC

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Gerrit-Change-Number: 50899
Gerrit-PatchSet: 13
Gerrit-Owner: Cliff Huang <cliff.huang@intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k@intel.com>
Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Selma Bensaid <selma.bensaid@intel.com>
Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: AndreX Andraos <andrex.andraos@intel.com>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Gerrit-CC: Shaunak Saha <shaunak.saha@intel.com>
Gerrit-MessageType: merged