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3 comments:

• File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h:

  • Patch Set #10, Line 33:

    #define GPP_B_DW0_1		0
    #define GPP_T_DW0_1		1
    #define GPP_A_DW0_1		2
    #define GPP_R_DW0_1		3
    #define GPD_DW0_1		4
    #define GPP_S_DW0_1		5
    #define GPP_H_DW0_1		6
    #define GPP_D_DW0_1		7
    #define GPP_U_DW0_1		8
    #define GPP_F_DW0_1		0xA
    #define GPP_C_DW0_1		0xB
    #define GPP_E_DW0_1		0xC
    /* For DW2*/
    #define GPP_G_DW2		0
    #define GPP_B_DW2		1
    #define GPP_A_DW2		2
    #define GPP_R_DW2		3
    #define GPP_S_DW2		4
    #define GPD_DW2			5
    #define GPP_H_DW2		6
    #define GPP_D_DW2		7
    #define GPP_F_DW2		8
    #define GPP_C_DW2		0xA
    #define GPP_E_DW2		0xB
    

    All hex or all decimal.

  • Patch Set #10, Line 380: /* TGL alternative native function pin mux */

    Need a bit more explanation why we need these macros.

• File src/soc/intel/tigerlake/include/soc/pmc.h:

  • Patch Set #10, Line 118:

    #define  PMC_GPP_B		0x0
    #define  PMC_GPP_T		0x1
    #define  PMC_GPP_A		0x2
    #define  PMC_GPP_S		0x3
    #define  PMC_GPP_H		0x4
    #define  PMC_GPP_D		0x5
    #define  PMC_GPP_U		0x6
    #define  PMC_GPP_VGPIO		0x7
    #define  PMC_GPD                0x8
    #define  PMC_GPP_C		0x9
    #define  PMC_GPP_F		0xA
    #define  PMC_GPP_HVCMOS		0xB
    #define  PMC_GPP_E		0xC
    #define  PMC_GPP_JTAG		0xD
    #define  PMC_GPP_R              0xE
    #define  PMC_GPP_SPI            0xF
    

    This order is wrong. I will push a proper fix.

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