Nico Huber has uploaded this change for review.
soc/intel/skylake: Unify serial IRQ options
We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In two cases KBLRVP8 and 11, we had conflicting settings in devicetree
and Kconfig. We'll maintain the devicetree state, although it might be
that coreboot overrode this earlier.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
---
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/variants/asuka/devicetree.cb
M src/mainboard/google/glados/variants/caroline/devicetree.cb
M src/mainboard/google/glados/variants/cave/devicetree.cb
M src/mainboard/google/glados/variants/chell/devicetree.cb
M src/mainboard/google/glados/variants/glados/devicetree.cb
M src/mainboard/google/glados/variants/lars/devicetree.cb
M src/mainboard/google/glados/variants/sentry/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/Kconfig
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/lpc.c
29 files changed, 16 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31596/1
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 66c1c53..2f275ac 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -46,7 +46,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 07a453d..bfabe29 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -81,7 +81,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb
index d365e8f..e0a792d 100644
--- a/src/mainboard/google/glados/variants/asuka/devicetree.cb
+++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb
@@ -38,7 +38,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "4" # 4s
register "PmConfigSlpSusMinAssert" = "3" # 4s
diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb
index cffb6df..0f5a911 100644
--- a/src/mainboard/google/glados/variants/caroline/devicetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb
@@ -48,7 +48,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb
index e0c7fc7..a9b28a8 100644
--- a/src/mainboard/google/glados/variants/cave/devicetree.cb
+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb
@@ -48,7 +48,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb
index 1b87cca..07467b3 100644
--- a/src/mainboard/google/glados/variants/chell/devicetree.cb
+++ b/src/mainboard/google/glados/variants/chell/devicetree.cb
@@ -48,7 +48,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb
index f4e09a6..d4266cc 100644
--- a/src/mainboard/google/glados/variants/glados/devicetree.cb
+++ b/src/mainboard/google/glados/variants/glados/devicetree.cb
@@ -48,7 +48,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb
index 56087ad..f3f5eab 100644
--- a/src/mainboard/google/glados/variants/lars/devicetree.cb
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -36,7 +36,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "4" # 4s
register "PmConfigSlpSusMinAssert" = "3" # 4s
diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb
index 0effbd7..5cce0f0 100644
--- a/src/mainboard/google/glados/variants/sentry/devicetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb
@@ -38,7 +38,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "4" # 4s
register "PmConfigSlpSusMinAssert" = "3" # 4s
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 5b49884..407c37d 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -54,7 +54,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 251cab8..7335c0a 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -51,7 +51,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 5d9c096..59cca29 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -50,7 +50,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 75a01c2..fed85b6 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -51,7 +51,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 4d9403c..ac52208 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -56,7 +56,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index c8e4008..4f58f40 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -54,7 +54,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 4713a81..d813cc1 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -51,7 +51,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index 51399dc..fcd5aab 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -54,8 +54,6 @@
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
register "PmConfigSlpAMinAssert" = "0x03"
- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
- register "SerialIrqConfigSirqEnable" = "0x01"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index 119767f..436a4ed 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -11,7 +11,7 @@
register "Heci3Enabled" = "0"
register "PmTimerDisabled" = "0"
- register "SerialIrqConfigSirqMode" = "0x01"
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Enable PCIE slot
register "PcieRpEnable[5]" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 9753c64..8dbaf68 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -10,7 +10,8 @@
register "ScsSdCardEnabled" = "0"
register "HeciEnabled" = "0"
register "PmTimerDisabled" = "0"
- register "SerialIrqConfigSirqMode" = "0x01"
+
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 4b720bf..ec1c11f 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -60,8 +60,6 @@
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
register "PmConfigSlpAMinAssert" = "0x03"
- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
- register "SerialIrqConfigSirqEnable" = "0x01"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index 197121e..524bcca 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -25,7 +25,6 @@
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select INTEL_LPSS_UART_FOR_CONSOLE
- select SERIRQ_CONTINUOUS_MODE
select SKYLAKE_SOC_PCH_H
select SOC_INTEL_SKYLAKE
select SUPERIO_NUVOTON_NCT6776
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 7036b28..8f78249 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -60,9 +60,7 @@
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
register "PmConfigSlpAMinAssert" = "0x03"
- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
- register "SerialIrqConfigSirqEnable" = "0x01"
- register "SerialIrqConfigSirqMode" = "0x01"
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index 399c643..a089712 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -61,7 +61,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "3" # 500ms
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index f9f7ef7..9bf0b98 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -61,7 +61,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "3" # 500ms
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 77d259b..53094b1 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -162,13 +162,6 @@
help
This option allows you to select MMIO Base Address of sideband bus.
-config SERIRQ_CONTINUOUS_MODE
- bool
- default n
- help
- If you set this option to y, the serial IRQ machine will be
- operated in continuous mode.
-
config SMM_RESERVED_SIZE
hex
default 0x200000
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index cbbfaaa..1f32a3e 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -22,6 +22,7 @@
#include <fsp/util.h>
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/acpi.h>
@@ -190,8 +191,9 @@
params->PmConfigPwrBtnOverridePeriod =
config->PmConfigPwrBtnOverridePeriod;
params->PmConfigPwrCycDur = config->PmConfigPwrCycDur;
- params->SerialIrqConfigSirqEnable = config->SerialIrqConfigSirqEnable;
- params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode;
+ params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF;
+ params->SerialIrqConfigSirqMode =
+ config->serirq_mode == SERIRQ_CONTINUOUS;
params->SerialIrqConfigStartFramePulse =
config->SerialIrqConfigStartFramePulse;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index f131a1a..a8ee064 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -24,6 +24,7 @@
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/chip.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
#include <stdint.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@@ -428,13 +429,7 @@
RESET_POWER_CYCLE_4S = 4,
} PmConfigPwrCycDur;
- /* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
- u8 SerialIrqConfigSirqEnable;
-
- enum {
- SERIAL_IRQ_QUIET_MODE = 0,
- SERIAL_IRQ_CONTINUOUS_MODE = 1,
- } SerialIrqConfigSirqMode;
+ enum serirq_mode serirq_mode;
enum {
SERIAL_IRQ_FRAME_PULSE_4CLK = 0,
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index f4e17c6..c9afeb4 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -26,6 +26,7 @@
#include <fsp/util.h>
#include <intelblocks/chip.h>
#include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
@@ -418,8 +419,8 @@
/* Indicate whether platform supports Voltage Margining */
params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable;
- params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
- params->PchSirqMode = config->SerialIrqConfigSirqMode;
+ params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
+ params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 8d97822..ae6c144 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -109,6 +109,8 @@
void lpc_soc_init(struct device *dev)
{
+ const config_t *const config = dev->chip_info;
+
/* Legacy initialization */
isa_dma_init();
reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
@@ -117,10 +119,7 @@
lpc_enable_pci_clk_cntl();
/* Set LPC Serial IRQ mode */
- if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
- lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
- else
- lpc_set_serirq_mode(SERIRQ_QUIET);
+ lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */
pch_enable_ioapic(dev);
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