HAOUAS Elyes has uploaded this change for review.
sb/intel/common: Improve code formatting
Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/common/madt.c
M src/southbridge/intel/common/rcba_pirq.c
M src/southbridge/intel/common/rtc.c
M src/southbridge/intel/common/smbus.c
M src/southbridge/intel/common/smihandler.c
6 files changed, 16 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/40258/1
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c
index 4c6cc63..e956965 100644
--- a/src/southbridge/intel/common/finalize.c
+++ b/src/southbridge/intel/common/finalize.c
@@ -15,8 +15,7 @@
{
const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
- if (CONFIG(LOCK_SPI_FLASH_RO) ||
- CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) {
+ if (CONFIG(LOCK_SPI_FLASH_RO) || CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) {
int i;
u32 lockmask = 1UL << 31;
if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS))
@@ -43,8 +42,7 @@
pci_or_config16(lpc_dev, D31F0_GEN_PMCON_1, SMI_LOCK);
- pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK,
- ACPI_BASE_LOCK | SLP_STR_POL_LOCK);
+ pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK, ACPI_BASE_LOCK | SLP_STR_POL_LOCK);
pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
@@ -54,8 +52,7 @@
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
- pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
- pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);
diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c
index 3385270..d425a74 100644
--- a/src/southbridge/intel/common/madt.c
+++ b/src/southbridge/intel/common/madt.c
@@ -11,8 +11,7 @@
current = acpi_create_madt_lapics(current);
/* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c
index 620d9fa..e1da606 100644
--- a/src/southbridge/intel/common/rcba_pirq.c
+++ b/src/southbridge/intel/common/rcba_pirq.c
@@ -16,8 +16,7 @@
D26IR, D27IR, D28IR, D29IR, D30IR, D31IR,
};
-enum pirq intel_common_map_pirq(const struct device *dev,
- const enum pci_pin pci_pin)
+enum pirq intel_common_map_pirq(const struct device *dev, const enum pci_pin pci_pin)
{
u8 slot = PCI_SLOT(dev->path.pci.devfn);
u8 shift = 4 * (pci_pin - PCI_INT_A);
@@ -25,8 +24,7 @@
u16 reg;
if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) {
- printk(BIOS_ERR,
- "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n",
+ printk(BIOS_ERR, "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n",
slot, pci_pin);
return PIRQ_NONE;
}
diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c
index f4ac9f0..26ca65c 100644
--- a/src/southbridge/intel/common/rtc.c
+++ b/src/southbridge/intel/common/rtc.c
@@ -19,8 +19,7 @@
int rtc_failure(void)
{
- return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3)
- & RTC_BATTERY_DEAD);
+ return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3) & RTC_BATTERY_DEAD);
}
void sb_rtc_init(void)
@@ -30,8 +29,7 @@
if (rtc_failed) {
if (CONFIG(ELOG))
elog_add_event(ELOG_TYPE_RTC_RESET);
- pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3,
- ~RTC_BATTERY_DEAD, 0);
+ pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0);
}
printk(BIOS_DEBUG, "RTC: failed = 0x%x\n", rtc_failed);
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index 17ac5110..222c4a4 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -110,8 +110,7 @@
return 0;
/* These status bits do not imply completion of transaction. */
- status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS |
- SMBHSTSTS_SMBALERT_STS);
+ status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | SMBHSTSTS_SMBALERT_STS);
return status != 0;
}
@@ -127,8 +126,7 @@
static int cb_err_from_stat(u8 status)
{
/* These status bits do not imply errors. */
- status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS |
- SMBHSTSTS_SMBALERT_STS);
+ status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | SMBHSTSTS_SMBALERT_STS);
if (status == SMBHSTSTS_INTR)
return 0;
@@ -182,8 +180,7 @@
} while (--loops && status == 0);
if (loops == 0)
- return recover_master(base,
- SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT);
+ return recover_master(base, SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT);
return 0;
}
@@ -199,8 +196,7 @@
} while (--loops && !host_completed(status));
if (loops == 0)
- return recover_master(base,
- SMBUS_WAIT_UNTIL_DONE_TIMEOUT);
+ return recover_master(base, SMBUS_WAIT_UNTIL_DONE_TIMEOUT);
return cb_err_from_stat(status);
}
@@ -317,8 +313,7 @@
/* Indicate that next byte is the last one. */
if (sw_drives_nak && (bytes + 1 >= max_bytes)) {
- host_and_or(base, SMBHSTCTL, 0xff,
- SMBHSTCNT_LAST_BYTE);
+ host_and_or(base, SMBHSTCTL, 0xff, SMBHSTCNT_LAST_BYTE);
}
}
@@ -421,8 +416,7 @@
/* Only since ICH5 */
static int has_i2c_read_command(void)
{
- if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) ||
- CONFIG(SOUTHBRIDGE_INTEL_I82801DX))
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || CONFIG(SOUTHBRIDGE_INTEL_I82801DX))
return 0;
return 1;
}
@@ -440,8 +434,7 @@
* some revision of PCH. Presumably hardware revisions that
* do not have i2c block write support internally set LSB.
*/
- ret = setup_command(base, I801_I2C_BLOCK_DATA,
- XMIT_WRITE(device));
+ ret = setup_command(base, I801_I2C_BLOCK_DATA, XMIT_WRITE(device));
if (ret < 0)
return ret;
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 7d4066d..9133a53 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -78,8 +78,7 @@
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
+ if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) {
unsigned int buses;
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
busmaster_disable_on_bus((buses >> 8) & 0xff);
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