Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai.
4 comments:
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #1, Line 72: register "PcieClkSrcUsage[0]" = "0x40"
you are right, this is all due to wrong naming in FSP, ideally this is CPU RP 1 getting PEG clk 0
Ack
Patch Set #1, Line 75: register "PcieClkSrcUsage[3]" = "0x41"
Same here, as far as I understand it, this configures PCH CLKSRC 3 to be used for CPU PCIe RP 2.
Ack
Patch Set #1, Line 76: register "PcieClkSrcUsage[4]" = "0x42"
Same here, as far as I understand it, this configures PCH CLKSRC 4 to be used for CPU PCIe RP 3.
Ack
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #2, Line 74: Enable CPU PCIE PEG Slot 1 and 2
Sure on it. […]
Ack
To view, visit change 49136. To unsubscribe, or for help writing mail filters, visit settings.