Patrick Georgi uploaded patch set #21 to the change originally created by Julien Viard de Galbert.

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soc/intel/denverton_ns: Implement PCIe post config + lock

- Configure PCIe maximum payload size to fix Intel SSD
- Lock Down PCIe Configuration

Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
---
M src/soc/intel/denverton_ns/lpc.c
1 file changed, 35 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/21

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