Maxim Polyakov has uploaded this change for review.
intelp2m: Rework register package
Split all methods between DW0 and DW1 to avoid the mistake of using any
DW0 method with DW1 receiver and make the code safer. Also make some
code style fixes.
Change-Id: Id64e2a5e29f1d561597004ac83d32e3c80c16ebd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
M util/intelp2m/fields/cb/cb.go
M util/intelp2m/fields/fsp/fsp.go
M util/intelp2m/fields/raw/raw.go
M util/intelp2m/fields/test/suite.go
M util/intelp2m/parser/template.go
M util/intelp2m/parser/template_test.go
M util/intelp2m/platforms/adl/macro.go
M util/intelp2m/platforms/apl/macro.go
M util/intelp2m/platforms/cnl/macro.go
M util/intelp2m/platforms/common/macro.go
D util/intelp2m/platforms/common/register.go
A util/intelp2m/platforms/common/register/bits/bits.go
A util/intelp2m/platforms/common/register/dw0.go
A util/intelp2m/platforms/common/register/dw1.go
A util/intelp2m/platforms/common/register/register.go
M util/intelp2m/platforms/lbg/macro.go
M util/intelp2m/platforms/snr/macro.go
17 files changed, 661 insertions(+), 609 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/70309/1
diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go
index 0c8988eb..031c83a 100644
--- a/util/intelp2m/fields/cb/cb.go
+++ b/util/intelp2m/fields/cb/cb.go
@@ -50,7 +50,7 @@
// DecodeDW0 - decode value of DW0 register
func (FieldMacros) DecodeDW0() {
macro := common.GetMacro()
- dw0 := macro.Register(common.PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
generate(
&field{
prefix: "PAD_FUNC",
@@ -133,7 +133,7 @@
// DecodeDW1 - decode value of DW1 register
func (FieldMacros) DecodeDW1() {
macro := common.GetMacro()
- dw1 := macro.Register(common.PAD_CFG_DW1)
+ dw1 := macro.GetRegisterDW1()
generate(
&field{
name: "PAD_CFG1_TOL_1V8",
diff --git a/util/intelp2m/fields/fsp/fsp.go b/util/intelp2m/fields/fsp/fsp.go
index b6224cd..db6b4ad 100644
--- a/util/intelp2m/fields/fsp/fsp.go
+++ b/util/intelp2m/fields/fsp/fsp.go
@@ -2,16 +2,16 @@
import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
-type FieldMacros struct {}
+type FieldMacros struct{}
// field - data structure for creating a new bitfield macro object
// configmap : map to select the current configuration
// value : the key value in the configmap
// override : overrides the function to generate the current bitfield macro
type field struct {
- configmap map[uint8]string
- value uint8
- override func(configuration map[uint8]string, value uint8)
+ configmap map[uint32]string
+ value uint32
+ override func(configuration map[uint32]string, value uint32)
}
// generate - wrapper for generating bitfield macros string
@@ -37,16 +37,18 @@
// DecodeDW0 - decode value of DW0 register
func (FieldMacros) DecodeDW0() {
macro := common.GetMacro()
- dw0 := macro.Register(common.PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
- ownershipStatus := func() uint8 {
- if macro.IsOwnershipDriver() { return 1 }
+ ownershipStatus := func() uint32 {
+ if macro.IsOwnershipDriver() {
+ return 1
+ }
return 0
}
generate(
- &field {
- configmap : map[uint8]string{
+ &field{
+ configmap: map[uint32]string{
0: "GpioPadModeGpio",
1: "GpioPadModeNative1",
2: "GpioPadModeNative2",
@@ -54,79 +56,79 @@
4: "GpioPadModeNative4",
5: "GpioPadModeNative5",
},
- value : dw0.GetPadMode(),
+ value: dw0.GetPadMode(),
},
- &field {
- configmap : map[uint8]string {
+ &field{
+ configmap: map[uint32]string{
0: "GpioHostOwnAcpi",
1: "GpioHostOwnGpio",
},
- value : ownershipStatus(),
+ value: ownershipStatus(),
},
- &field {
- configmap : map[uint8]string {
- 0: "GpioDirInOut",
- 1: "GpioDirIn",
- 2: "GpioDirOut",
- 3: "GpioDirNone",
- 1 << 4 | 0: "GpioDirInInvOut",
- 1 << 4 | 1: "GpioDirInInv",
+ &field{
+ configmap: map[uint32]string{
+ 0: "GpioDirInOut",
+ 1: "GpioDirIn",
+ 2: "GpioDirOut",
+ 3: "GpioDirNone",
+ (1 << 4): "GpioDirInInvOut",
+ (1 << 4) | 1: "GpioDirInInv",
},
- value : dw0.GetRxInvert() << 4 | dw0.GetGPIORxTxDisableStatus(),
+ value: dw0.GetRxInvert()<<4 | dw0.GetGPIORxTxDisableStatus(),
},
- &field {
- configmap : map[uint8]string {
+ &field{
+ configmap: map[uint32]string{
0: "GpioOutLow",
1: "GpioOutHigh",
},
- value : dw0.GetGPIOTXState(),
+ value: dw0.GetGPIOTXState(),
},
- &field {
- configmap : map[uint8]string {
+ &field{
+ configmap: map[uint32]string{
1 << 0: "GpioIntNmi",
1 << 1: "GpioIntSmi",
1 << 2: "GpioIntSci",
1 << 3: "GpioIntApic",
},
- override : func(configmap map[uint8]string, value uint8) {
- mask := dw0.GetGPIOInputRouteIOxAPIC() << 3 |
- dw0.GetGPIOInputRouteSCI() << 2 |
- dw0.GetGPIOInputRouteSMI() << 1 |
- dw0.GetGPIOInputRouteNMI()
+ override: func(configmap map[uint32]string, value uint32) {
+ mask := dw0.GetGPIOInputRouteIOxAPIC()<<3 |
+ dw0.GetGPIOInputRouteSCI()<<2 |
+ dw0.GetGPIOInputRouteSMI()<<1 |
+ dw0.GetGPIOInputRouteNMI()
if mask == 0 {
macro.Add("GpioIntDis | ")
return
}
for bit, fieldmacro := range configmap {
- if mask & bit != 0 {
+ if mask&bit != 0 {
macro.Add(fieldmacro).Add(" | ")
}
}
},
},
- &field {
- configmap : map[uint8]string {
+ &field{
+ configmap: map[uint32]string{
0: "GpioIntLevel",
1: "GpioIntEdge",
2: "GpioIntLvlEdgDis",
3: "GpioIntBothEdge",
},
- value : dw0.GetRXLevelEdgeConfiguration(),
+ value: dw0.GetRXLevelEdgeConfiguration(),
},
- &field {
- configmap : map[uint8]string {
- 0: "GpioResetPwrGood", // TODO: Has multiple values (to GPP and GPD)
+ &field{
+ configmap: map[uint32]string{
+ 0: "GpioResetPwrGood", // TODO: Has multiple values (to GPP and GPD)
1: "GpioHostDeepReset",
2: "GpioPlatformReset",
3: "GpioResumeReset",
},
- value : dw0.GetResetConfig(),
+ value: dw0.GetResetConfig(),
},
)
}
@@ -134,18 +136,18 @@
// DecodeDW1 - decode value of DW1 register
func (FieldMacros) DecodeDW1() {
macro := common.GetMacro()
- dw1 := macro.Register(common.PAD_CFG_DW1)
+ dw1 := macro.GetRegisterDW1()
generate(
- &field {
- override : func(configmap map[uint8]string, value uint8) {
+ &field{
+ override: func(configmap map[uint32]string, value uint32) {
if dw1.GetPadTol() != 0 {
macro.Add("GpioTolerance1v8 | ")
}
},
},
- &field {
- configmap : map[uint8]string {
+ &field{
+ configmap: map[uint32]string{
0x0: "GpioTermNone",
0x2: "GpioTermWpd5K",
0x4: "GpioTermWpd20K",
@@ -156,7 +158,7 @@
0xd: "GpioTermWpu1K2K",
0xf: "GpioTermNative",
},
- value : dw1.GetTermination(),
+ value: dw1.GetTermination(),
},
)
}
diff --git a/util/intelp2m/fields/raw/raw.go b/util/intelp2m/fields/raw/raw.go
index fbac5b5..4efccd5 100644
--- a/util/intelp2m/fields/raw/raw.go
+++ b/util/intelp2m/fields/raw/raw.go
@@ -1,22 +1,21 @@
package raw
import (
- "fmt"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
)
-type FieldMacros struct {}
+type FieldMacros struct{}
func (FieldMacros) DecodeDW0() {
macro := common.GetMacro()
- // Do not decode, print as is.
- macro.Add(fmt.Sprintf("0x%0.8x", macro.Register(common.PAD_CFG_DW0).ValueGet()))
+ dw0 := macro.GetRegisterDW0()
+ macro.Add(dw0.String())
}
func (FieldMacros) DecodeDW1() {
macro := common.GetMacro()
- // Do not decode, print as is.
- macro.Add(fmt.Sprintf("0x%0.8x", macro.Register(common.PAD_CFG_DW1).ValueGet()))
+ dw1 := macro.GetRegisterDW1()
+ macro.Add(dw1.String())
}
// GenerateString - generates the entire string of bitfield macros.
diff --git a/util/intelp2m/fields/test/suite.go b/util/intelp2m/fields/test/suite.go
index a61062e..3041de2 100644
--- a/util/intelp2m/fields/test/suite.go
+++ b/util/intelp2m/fields/test/suite.go
@@ -29,13 +29,13 @@
t.Run(label, func(t *testing.T) {
platform := snr.PlatformSpecific{}
macro := common.GetInstanceMacro(platform, decoderIf)
- dw0 := macro.Register(common.PAD_CFG_DW0)
- dw1 := macro.Register(common.PAD_CFG_DW1)
+ dw0 := macro.GetRegisterDW0()
+ dw1 := macro.GetRegisterDW1()
for _, tc := range suite {
macro.Clear()
macro.PadIdSet("").SetPadOwnership(tc.Ownership)
- dw0.ValueSet(tc.DW0)
- dw1.ValueSet(tc.DW1)
+ dw0.Value = tc.DW0
+ dw1.Value = tc.DW1
macro.Fields.GenerateString()
if err := tc.Check(macro.Get()); err != nil {
t.Errorf("Test failed: %v", err)
diff --git a/util/intelp2m/parser/template.go b/util/intelp2m/parser/template.go
index e7efa73..49b938f 100644
--- a/util/intelp2m/parser/template.go
+++ b/util/intelp2m/parser/template.go
@@ -6,7 +6,7 @@
"unicode"
)
-const INTSEL_MASK uint32 = 0xffffff00
+const IntSelMask uint32 = 0xffffff00
type template func(string, *string, *string, *uint32, *uint32) int
@@ -57,7 +57,7 @@
*function += "/" + fields[i]
}
// clear RO Interrupt Select (INTSEL)
- *dw1 &= INTSEL_MASK
+ *dw1 &= IntSelMask
}
return 0
}
diff --git a/util/intelp2m/parser/template_test.go b/util/intelp2m/parser/template_test.go
index 95f8ebf..9abdd72 100644
--- a/util/intelp2m/parser/template_test.go
+++ b/util/intelp2m/parser/template_test.go
@@ -30,9 +30,9 @@
} else if dw0 != ref_dw0 {
t.Errorf("dw0 from '%s':\nExpects: '0x%08x'\nActually: '0x%08x'\n\n",
line, ref_dw0, dw0)
- } else if dw1 != (ref_dw1 & parser.INTSEL_MASK) {
+ } else if dw1 != (ref_dw1 & parser.IntSelMask) {
t.Errorf("dw1 from '%s':\nExpects: '0x%08x'\nActually: '0x%08x'\n\n",
- line, (ref_dw1 & parser.INTSEL_MASK), dw1)
+ line, (ref_dw1 & parser.IntSelMask), dw1)
}
})
}
diff --git a/util/intelp2m/platforms/adl/macro.go b/util/intelp2m/platforms/adl/macro.go
index 2c4b5d8..7c4f435 100644
--- a/util/intelp2m/platforms/adl/macro.go
+++ b/util/intelp2m/platforms/adl/macro.go
@@ -7,6 +7,7 @@
"review.coreboot.org/coreboot.git/util/intelp2m/fields"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
)
@@ -15,12 +16,6 @@
PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
)
-const (
- PAD_CFG_DW0 = common.PAD_CFG_DW0
- PAD_CFG_DW1 = common.PAD_CFG_DW1
- MAX_DW_NUM = common.MAX_DW_NUM
-)
-
type InheritanceMacro interface {
Pull()
GpiMacroAdd()
@@ -43,22 +38,22 @@
return
}
- dw0 := macro.Register(PAD_CFG_DW0)
- var remapping = map[uint8]uint32{
- 0: common.RST_RSMRST << common.PadRstCfgShift,
- 1: common.RST_DEEP << common.PadRstCfgShift,
- 2: common.RST_PLTRST << common.PadRstCfgShift,
- 3: common.RST_PWROK << common.PadRstCfgShift,
+ dw0 := macro.GetRegisterDW0()
+ remapping := map[uint32]uint32{
+ 0: (bits.RstCfgRSMRST << bits.DW0PadRstCfg),
+ 1: (bits.RstCfgDEEP << bits.DW0PadRstCfg),
+ 2: (bits.RstCfgPLTRST << bits.DW0PadRstCfg),
+ 3: (bits.RstCfgPWROK << bits.DW0PadRstCfg),
}
resetsrc, valid := remapping[dw0.GetResetConfig()]
if valid {
// dw0.SetResetConfig(resetsrc)
- ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
- dw0.ValueSet(ResetConfigFieldVal)
+ ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+ dw0.Value = ResetConfigFieldVal
} else {
fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
}
- dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+ dw0.CntrMaskFieldsClear(0b11 << bits.DW0PadRstCfg)
}
// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -88,11 +83,11 @@
}
// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
// return: string of macro
// error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
macro := common.GetInstanceMacro(
PlatformSpecific{
InheritanceMacro: cnl.PlatformSpecific{
@@ -102,10 +97,17 @@
fields.InterfaceGet(),
)
macro.Clear()
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
- macro.Register(PAD_CFG_DW1).CntrMaskFieldsClear(common.AllFields)
+ dw0 := macro.GetRegisterDW0()
+ dw0.CntrMaskFieldsClear(bits.All32)
+
+ dw1 := macro.GetRegisterDW1()
+ dw1.CntrMaskFieldsClear(bits.All32)
+
+ dw0.Value = dw0Val
+ dw1.Value = dw1Val
+
+ dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+ dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
macro.PadIdSet(id).SetPadOwnership(ownership)
- macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
- macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
return macro.Generate()
}
diff --git a/util/intelp2m/platforms/apl/macro.go b/util/intelp2m/platforms/apl/macro.go
index 6ed1eec..7b2ce63 100644
--- a/util/intelp2m/platforms/apl/macro.go
+++ b/util/intelp2m/platforms/apl/macro.go
@@ -7,6 +7,7 @@
"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
"review.coreboot.org/coreboot.git/util/intelp2m/fields"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
)
const (
@@ -15,12 +16,6 @@
)
const (
- PAD_CFG_DW0 = common.PAD_CFG_DW0
- PAD_CFG_DW1 = common.PAD_CFG_DW1
- MAX_DW_NUM = common.MAX_DW_NUM
-)
-
-const (
PULL_NONE = 0x0 // 0 000: none
PULL_DN_5K = 0x2 // 0 010: 5k wpd (Only available on SMBus GPIOs)
PULL_DN_20K = 0x4 // 0 100: 20k wpd
@@ -42,8 +37,8 @@
// return: macro
func (PlatformSpecific) Pull() {
macro := common.GetMacro()
- dw1 := macro.Register(PAD_CFG_DW1)
- var pull = map[uint8]string{
+ dw1 := macro.GetRegisterDW1()
+ var pull = map[uint32]string{
PULL_NONE: "NONE",
PULL_DN_5K: "DN_5K",
PULL_DN_20K: "DN_20K",
@@ -53,10 +48,9 @@
PULL_UP_667: "UP_667",
PULL_NATIVE: "NATIVE",
}
- terminationFieldValue := dw1.GetTermination()
- str, valid := pull[terminationFieldValue]
- if !valid {
- str = strconv.Itoa(int(terminationFieldValue))
+ str, exist := pull[dw1.GetTermination()]
+ if !exist {
+ str = strconv.Itoa(int(dw1.GetTermination()))
fmt.Println("Error", macro.PadIdGet(), " invalid TERM value = ", str)
}
macro.Separator().Add(str)
@@ -65,8 +59,8 @@
// Generate macro to cause peripheral IRQ when configured in GPIO input mode
func ioApicRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- dw1 := macro.Register(PAD_CFG_DW1)
+ dw0 := macro.GetRegisterDW0()
+ dw1 := macro.GetRegisterDW1()
if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
return false
}
@@ -86,7 +80,7 @@
// Generate macro to cause NMI when configured in GPIO input mode
func nmiRoute() bool {
macro := common.GetMacro()
- if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
+ if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
return false
}
// e.g. PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
@@ -97,8 +91,8 @@
// Generate macro to cause SCI when configured in GPIO input mode
func sciRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- dw1 := macro.Register(PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
+ dw1 := macro.GetRegisterDW1()
if dw0.GetGPIOInputRouteSCI() == 0 {
return false
}
@@ -120,8 +114,8 @@
// Generate macro to cause SMI when configured in GPIO input mode
func smiRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- dw1 := macro.Register(PAD_CFG_DW1)
+ dw0 := macro.GetRegisterDW0()
+ dw1 := macro.GetRegisterDW1()
if dw0.GetGPIOInputRouteSMI() == 0 {
return false
}
@@ -159,7 +153,7 @@
switch config, argc := p2m.SettingsGet(), len(ids); argc {
case 0:
- dw1 := macro.Register(PAD_CFG_DW1)
+ dw1 := macro.GetRegisterDW1()
isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0
isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0
if isIOStandbyStateUsed && !isIOStandbyTerminationUsed {
@@ -189,15 +183,15 @@
default:
// Clear the control mask so that the check fails and "Advanced" macro is
// generated
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+ macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
}
}
// Adds PAD_CFG_GPO macro with arguments
func (PlatformSpecific) GpoMacroAdd() {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- dw1 := macro.Register(PAD_CFG_DW1)
+ dw0 := macro.GetRegisterDW0()
+ dw1 := macro.GetRegisterDW1()
term := dw1.GetTermination()
macro.Set("PAD_CFG")
@@ -219,22 +213,22 @@
}
macro.Add("),")
- if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
+ if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
// ignore if trig = OFF is not set
- dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+ dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxLevelEdgeConfiguration])
}
}
// Adds PAD_CFG_NF macro with arguments
func (PlatformSpecific) NativeFunctionMacroAdd() {
macro := common.GetMacro()
- dw1 := macro.Register(PAD_CFG_DW1)
+ dw1 := macro.GetRegisterDW1()
isIOStandbyStateUsed := dw1.GetIOStandbyState() != 0
isIOStandbyTerminationUsed := dw1.GetIOStandbyTermination() != 0
macro.Set("PAD_CFG_NF")
if !isIOStandbyTerminationUsed && isIOStandbyStateUsed {
- if dw1.GetIOStandbyState() == common.StandbyIgnore {
+ if dw1.GetIOStandbyState() == bits.IOStateStandbyIgnore {
// PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1),
macro.Add("_IOSTANDBY_IGNORE(").Id().Pull().Rstsrc().Padfn()
} else {
@@ -250,27 +244,26 @@
}
macro.Add("),")
- if dw0 := macro.Register(PAD_CFG_DW0); dw0.GetGPIORxTxDisableStatus() != 0 {
+ if dw0 := macro.GetRegisterDW0(); dw0.GetGPIORxTxDisableStatus() != 0 {
// Since the bufbis parameter will be ignored for NF, we should clear
// the corresponding bits in the control mask.
- dw0.CntrMaskFieldsClear(common.RxTxBufDisableMask)
+ dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxTxBufDisable])
}
}
// Adds PAD_NC macro
func (PlatformSpecific) NoConnMacroAdd() {
macro := common.GetMacro()
- dw1 := macro.Register(PAD_CFG_DW1)
- if dw1.GetIOStandbyState() == common.TxDRxE {
- dw0 := macro.Register(PAD_CFG_DW0)
+ dw0, dw1 := macro.GetRegisterDW0(), macro.GetRegisterDW1()
+ if dw1.GetIOStandbyState() == bits.IOStateTxDRxE {
// See comments in sunrise/macro.go : NoConnMacroAdd()
- if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
- dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+ if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+ dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0RxLevelEdgeConfiguration])
}
if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP
- dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+ dw0.CntrMaskFieldsClear(bits.DW0[bits.DW0PadRstCfg])
}
// PAD_NC(OSC_CLK_OUT_1, DN_20K)
@@ -287,17 +280,24 @@
}
// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
// return: string of macro
// error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet())
- // use platform-specific interface in Macro struct
+ macro.Clear()
+ dw0 := macro.GetRegisterDW0()
+ dw0.CntrMaskFieldsClear(bits.All32)
+
+ dw1 := macro.GetRegisterDW1()
+ dw1.CntrMaskFieldsClear(bits.All32)
+
+ dw0.Value = dw0Val
+ dw1.Value = dw1Val
+
+ dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+ dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
macro.PadIdSet(id).SetPadOwnership(ownership)
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
- macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
- macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
return macro.Generate()
}
diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go
index 08574de..0d2ba46 100644
--- a/util/intelp2m/platforms/cnl/macro.go
+++ b/util/intelp2m/platforms/cnl/macro.go
@@ -7,6 +7,7 @@
"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
"review.coreboot.org/coreboot.git/util/intelp2m/fields"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
)
@@ -15,12 +16,6 @@
PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
)
-const (
- PAD_CFG_DW0 = common.PAD_CFG_DW0
- PAD_CFG_DW1 = common.PAD_CFG_DW1
- MAX_DW_NUM = common.MAX_DW_NUM
-)
-
type InheritanceMacro interface {
GpoMacroAdd()
NativeFunctionMacroAdd()
@@ -44,29 +39,30 @@
return
}
- dw0 := macro.Register(PAD_CFG_DW0)
- var remapping = map[uint8]uint32{
- 0: common.RST_RSMRST << common.PadRstCfgShift,
- 1: common.RST_DEEP << common.PadRstCfgShift,
- 2: common.RST_PLTRST << common.PadRstCfgShift,
+ dw0 := macro.GetRegisterDW0()
+ var remapping = map[uint32]uint32{
+ 0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+ 1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+ 2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
}
resetsrc, valid := remapping[dw0.GetResetConfig()]
if valid {
// dw0.SetResetConfig(resetsrc)
- ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
- dw0.ValueSet(ResetConfigFieldVal)
+ ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+ dw0.Value = ResetConfigFieldVal
} else {
fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
}
- dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+ mask := bits.DW0[bits.DW0PadRstCfg]
+ dw0.CntrMaskFieldsClear(mask)
}
// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
// as a new argument
func (PlatformSpecific) Pull() {
macro := common.GetMacro()
- dw1 := macro.Register(PAD_CFG_DW1)
- var pull = map[uint8]string{
+ dw1 := macro.GetRegisterDW1()
+ var pull = map[uint32]string{
0x0: "NONE",
0x2: "DN_5K",
0x4: "DN_20K",
@@ -91,7 +87,7 @@
// Generate macro to cause peripheral IRQ when configured in GPIO input mode
func ioApicRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
return false
}
@@ -105,7 +101,7 @@
// Generate macro to cause NMI when configured in GPIO input mode
func nmiRoute() bool {
macro := common.GetMacro()
- if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
+ if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
return false
}
// PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
@@ -116,8 +112,7 @@
// Generate macro to cause SCI when configured in GPIO input mode
func sciRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- if dw0.GetGPIOInputRouteSCI() == 0 {
+ if macro.GetRegisterDW0().GetGPIOInputRouteSCI() == 0 {
return false
}
// PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
@@ -128,8 +123,8 @@
// Generate macro to cause SMI when configured in GPIO input mode
func smiRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- if dw0.GetGPIOInputRouteSMI() == 0 {
+
+ if macro.GetRegisterDW0().GetGPIOInputRouteSMI() == 0 {
return false
}
// PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv)
@@ -175,7 +170,7 @@
default:
// Clear the control mask so that the check fails and "Advanced" macro is
// generated
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+ macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
}
}
@@ -195,18 +190,29 @@
}
// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
// return: string of macro
// error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
- macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}},
- fields.InterfaceGet())
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
+ macro := common.GetInstanceMacro(
+ PlatformSpecific{
+ InheritanceMacro: snr.PlatformSpecific{},
+ },
+ fields.InterfaceGet(),
+ )
macro.Clear()
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+ dw0 := macro.GetRegisterDW0()
+ dw0.CntrMaskFieldsClear(bits.All32)
+
+ dw1 := macro.GetRegisterDW1()
+ dw1.CntrMaskFieldsClear(bits.All32)
+
+ dw0.Value = dw0Val
+ dw1.Value = dw1Val
+
+ dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+ dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
macro.PadIdSet(id).SetPadOwnership(ownership)
- macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
- macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
return macro.Generate()
}
diff --git a/util/intelp2m/platforms/common/macro.go b/util/intelp2m/platforms/common/macro.go
index 02cbed9..0acede3 100644
--- a/util/intelp2m/platforms/common/macro.go
+++ b/util/intelp2m/platforms/common/macro.go
@@ -1,10 +1,13 @@
package common
import (
+ "fmt"
"strconv"
"sync"
"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register"
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
)
type Fields interface {
@@ -18,41 +21,6 @@
PAD_OWN_DRIVER = 1
)
-const (
- TxLASTRxE = 0x0
- Tx0RxDCRx0 = 0x1
- Tx0RxDCRx1 = 0x2
- Tx1RxDCRx0 = 0x3
- Tx1RxDCRx1 = 0x4
- Tx0RxE = 0x5
- Tx1RxE = 0x6
- HIZCRx0 = 0x7
- HIZCRx1 = 0x8
- TxDRxE = 0x9
- StandbyIgnore = 0xf
-)
-
-const (
- IOSTERM_SAME = 0x0
- IOSTERM_DISPUPD = 0x1
- IOSTERM_ENPD = 0x2
- IOSTERM_ENPU = 0x3
-)
-
-const (
- TRIG_LEVEL = 0
- TRIG_EDGE_SINGLE = 1
- TRIG_OFF = 2
- TRIG_EDGE_BOTH = 3
-)
-
-const (
- RST_PWROK = 0
- RST_DEEP = 1
- RST_PLTRST = 2
- RST_RSMRST = 3
-)
-
// PlatformSpecific - platform-specific interface
type PlatformSpecific interface {
RemmapRstSrc()
@@ -70,7 +38,8 @@
// Reg : structure of configuration register values and their masks
type Macro struct {
Platform PlatformSpecific
- Reg [MAX_DW_NUM]Register
+ DW0 register.DW0
+ DW1 register.DW1
padID string
str string
ownership uint8
@@ -110,10 +79,12 @@
return macro.ownership == PAD_OWN_DRIVER
}
-// returns <Register> data configuration structure
-// number : register number
-func (macro *Macro) Register(number uint8) *Register {
- return ¯o.Reg[number]
+func (macro *Macro) GetRegisterDW0() *register.DW0 {
+ return ¯o.DW0
+}
+
+func (macro *Macro) GetRegisterDW1() *register.DW1 {
+ return ¯o.DW1
}
// add a string to macro
@@ -158,14 +129,18 @@
// Adds the PADRSTCFG parameter from DW0 to the macro as a new argument
// return: Macro
func (macro *Macro) Rstsrc() *Macro {
- dw0 := macro.Register(PAD_CFG_DW0)
- var resetsrc = map[uint8]string{
- 0: "PWROK",
- 1: "DEEP",
- 2: "PLTRST",
- 3: "RSMRST",
+ dw0 := macro.GetRegisterDW0()
+ resetsrc := map[uint32]string{
+ 0b00: "PWROK",
+ 0b01: "DEEP",
+ 0b10: "PLTRST",
+ 0b11: "RSMRST",
}
- return macro.Separator().Add(resetsrc[dw0.GetResetConfig()])
+ source, exist := resetsrc[dw0.GetResetConfig()]
+ if !exist {
+ source = "ERROR"
+ }
+ return macro.Separator().Add(source)
}
// Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument
@@ -178,44 +153,51 @@
// Adds Pad GPO value to macro string as a new argument
// return: Macro
func (macro *Macro) Val() *Macro {
- dw0 := macro.Register(PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
return macro.Separator().Add(strconv.Itoa(int(dw0.GetGPIOTXState())))
}
// Adds Pad GPO value to macro string as a new argument
// return: Macro
func (macro *Macro) Trig() *Macro {
- dw0 := macro.Register(PAD_CFG_DW0)
- var trig = map[uint8]string{
- 0x0: "LEVEL",
- 0x1: "EDGE_SINGLE",
- 0x2: "OFF",
- 0x3: "EDGE_BOTH",
+ dw0 := macro.GetRegisterDW0()
+ trig := map[uint32]string{
+ 0b00: "LEVEL",
+ 0b01: "EDGE_SINGLE",
+ 0b10: "OFF",
+ 0b11: "EDGE_BOTH",
}
- return macro.Separator().Add(trig[dw0.GetRXLevelEdgeConfiguration()])
+ level, exist := trig[dw0.GetRXLevelEdgeConfiguration()]
+ if !exist {
+ level = "ERROR"
+ }
+ return macro.Separator().Add(level)
}
// Adds Pad Polarity Inversion Stage (RXINV) to macro string as a new argument
// return: Macro
func (macro *Macro) Invert() *Macro {
- macro.Separator()
- if macro.Register(PAD_CFG_DW0).GetRxInvert() != 0 {
- return macro.Add("INVERT")
+ if macro.GetRegisterDW0().GetRxInvert() != 0 {
+ return macro.Separator().Add("INVERT")
}
- return macro.Add("NONE")
+ return macro.Separator().Add("NONE")
}
// Adds input/output buffer state
// return: Macro
func (macro *Macro) Bufdis() *Macro {
- var buffDisStat = map[uint8]string{
- 0x0: "NO_DISABLE", // both buffers are enabled
- 0x1: "TX_DISABLE", // output buffer is disabled
- 0x2: "RX_DISABLE", // input buffer is disabled
- 0x3: "TX_RX_DISABLE", // both buffers are disabled
+ dw0 := macro.GetRegisterDW0()
+ states := map[uint32]string{
+ 0b00: "NO_DISABLE", // both buffers are enabled
+ 0b01: "TX_DISABLE", // output buffer is disabled
+ 0b10: "RX_DISABLE", // input buffer is disabled
+ 0b11: "TX_RX_DISABLE", // both buffers are disabled
}
- state := macro.Register(PAD_CFG_DW0).GetGPIORxTxDisableStatus()
- return macro.Separator().Add(buffDisStat[state])
+ state, exist := states[dw0.GetGPIORxTxDisableStatus()]
+ if !exist {
+ state = "ERROR"
+ }
+ return macro.Separator().Add(state)
}
// Adds macro to set the host software ownership
@@ -230,10 +212,9 @@
//Adds pad native function (PMODE) as a new argument
//return: Macro
func (macro *Macro) Padfn() *Macro {
- dw0 := macro.Register(PAD_CFG_DW0)
- nfnum := int(dw0.GetPadMode())
- if nfnum != 0 {
- return macro.Separator().Add("NF" + strconv.Itoa(nfnum))
+ dw0 := macro.GetRegisterDW0()
+ if number := dw0.GetPadMode(); number != 0 {
+ return macro.Separator().Add(fmt.Sprintf("NF%d", number))
}
// GPIO used only for PAD_FUNC(x) macro
return macro.Add("GPIO")
@@ -242,44 +223,49 @@
// Add a line to the macro that defines IO Standby State
// return: macro
func (macro *Macro) IOSstate() *Macro {
- var stateMacro = map[uint8]string{
- TxLASTRxE: "TxLASTRxE",
- Tx0RxDCRx0: "Tx0RxDCRx0",
- Tx0RxDCRx1: "Tx0RxDCRx1",
- Tx1RxDCRx0: "Tx1RxDCRx0",
- Tx1RxDCRx1: "Tx1RxDCRx1",
- Tx0RxE: "Tx0RxE",
- Tx1RxE: "Tx1RxE",
- HIZCRx0: "HIZCRx0",
- HIZCRx1: "HIZCRx1",
- TxDRxE: "TxDRxE",
- StandbyIgnore: "IGNORE",
+ states := map[uint32]string{
+ bits.IOStateTxLASTRxE: "TxLASTRxE",
+ bits.IOStateTx0RxDCRx0: "Tx0RxDCRx0",
+ bits.IOStateTx0RxDCRx1: "Tx0RxDCRx1",
+ bits.IOStateTx1RxDCRx0: "Tx1RxDCRx0",
+ bits.IOStateTx1RxDCRx1: "Tx1RxDCRx1",
+ bits.IOStateTx0RxE: "Tx0RxE",
+ bits.IOStateTx1RxE: "Tx1RxE",
+ bits.IOStateHIZCRx0: "HIZCRx0",
+ bits.IOStateHIZCRx1: "HIZCRx1",
+ bits.IOStateTxDRxE: "TxDRxE",
+ bits.IOStateStandbyIgnore: "IGNORE",
}
- dw1 := macro.Register(PAD_CFG_DW1)
- str, valid := stateMacro[dw1.GetIOStandbyState()]
- if !valid {
+ dw1 := macro.GetRegisterDW1()
+ state, exist := states[dw1.GetIOStandbyState()]
+ if !exist {
// ignore setting for incorrect value
- str = "IGNORE"
+ state = "ERROR"
}
- return macro.Separator().Add(str)
+ return macro.Separator().Add(state)
}
// Add a line to the macro that defines IO Standby Termination
// return: macro
func (macro *Macro) IOTerm() *Macro {
- var ioTermMacro = map[uint8]string{
- IOSTERM_SAME: "SAME",
- IOSTERM_DISPUPD: "DISPUPD",
- IOSTERM_ENPD: "ENPD",
- IOSTERM_ENPU: "ENPU",
+ dw1 := macro.GetRegisterDW1()
+ terminations := map[uint32]string{
+ bits.IOTermSAME: "SAME",
+ bits.IOTermDISPUPD: "DISPUPD",
+ bits.IOTermENPD: "ENPD",
+ bits.IOTermENPU: "ENPU",
}
- dw1 := macro.Register(PAD_CFG_DW1)
- return macro.Separator().Add(ioTermMacro[dw1.GetIOStandbyTermination()])
+ termination, exist := terminations[dw1.GetIOStandbyTermination()]
+ if !exist {
+ termination = "ERROR"
+ }
+ return macro.Separator().Add(termination)
}
// Check created macro
func (macro *Macro) check() *Macro {
- if !macro.Register(PAD_CFG_DW0).MaskCheck() {
+ dw0 := macro.GetRegisterDW0()
+ if !dw0.MaskCheck() {
return macro.GenerateFields()
}
return macro
@@ -293,35 +279,42 @@
return macro
}
-// DecodeIgnored - Add info about ignored field mask
-// reg : PAD_CFG_DW0 or PAD_CFG_DW1 register
-func (macro *Macro) DecodeIgnored(reg uint8) *Macro {
- var decode = map[uint8]func(){
- PAD_CFG_DW0: macro.Fields.DecodeDW0,
- PAD_CFG_DW1: macro.Fields.DecodeDW1,
- }
- decodefn, valid := decode[reg]
- if !valid || p2m.SettingsGet().Field == p2m.FspFlds {
+func (macro *Macro) DecodeIgnoredFieldsDW0() *Macro {
+ if p2m.SettingsGet().Field == p2m.FspFlds {
return macro
}
- dw := macro.Register(reg)
- ignored := dw.IgnoredFieldsGet()
- if ignored != 0 {
- temp := dw.ValueGet()
- dw.ValueSet(ignored)
- regnum := strconv.Itoa(int(reg))
- macro.Add("/* DW" + regnum + ": ")
- decodefn()
+ dw0 := macro.GetRegisterDW0()
+ if ignored := dw0.IgnoredFieldsGet(); ignored != 0 {
+ saved := dw0.Value
+ dw0.Value = ignored
+ macro.Add("/* DW0: ")
+ macro.Fields.DecodeDW0()
macro.Add(" - IGNORED */\n\t")
- dw.ValueSet(temp)
+ dw0.Value = saved
+ }
+ return macro
+}
+
+func (macro *Macro) DecodeIgnoredFieldsDW1() *Macro {
+ if p2m.SettingsGet().Field == p2m.FspFlds {
+ return macro
+ }
+ dw1 := macro.GetRegisterDW1()
+ if ignored := dw1.IgnoredFieldsGet(); ignored != 0 {
+ saved := dw1.Value
+ dw1.Value = ignored
+ macro.Add("/* DW0: ")
+ macro.DecodeDW1()
+ macro.Add(" - IGNORED */\n\t")
+ dw1.Value = saved
}
return macro
}
// GenerateFields - generate bitfield macros
func (macro *Macro) GenerateFields() *Macro {
- dw0 := macro.Register(PAD_CFG_DW0)
- dw1 := macro.Register(PAD_CFG_DW1)
+ dw0 := macro.GetRegisterDW0()
+ dw1 := macro.GetRegisterDW1()
// Get mask of ignored bit fields.
dw0Ignored := dw0.IgnoredFieldsGet()
@@ -336,7 +329,8 @@
reference := macro.Get()
macro.Clear()
/* DW0 : PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1 - IGNORED */
- macro.DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1)
+ macro.DecodeIgnoredFieldsDW0()
+ macro.DecodeIgnoredFieldsDW1()
if config.GenLevel >= 4 {
/* PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), */
macro.Add("/* ").Add(reference).Add(" */\n\t")
@@ -345,11 +339,11 @@
if config.IgnoredFields {
// Consider bit fields that should be ignored when regenerating
// advansed macros
- var tempVal uint32 = dw0.ValueGet() & ^dw0Ignored
- dw0.ValueSet(tempVal)
+ tempVal := dw0.Value & ^dw0Ignored
+ dw0.Value = tempVal
- tempVal = dw1.ValueGet() & ^dw1Ignored
- dw1.ValueSet(tempVal)
+ tempVal = dw1.Value & ^dw1Ignored
+ dw1.Value = tempVal
}
macro.Fields.GenerateString()
@@ -358,7 +352,7 @@
// Generate macro for bi-directional GPIO port
func (macro *Macro) Bidirection() {
- dw1 := macro.Register(PAD_CFG_DW1)
+ dw1 := macro.GetRegisterDW1()
ios := dw1.GetIOStandbyState() != 0 || dw1.GetIOStandbyTermination() != 0
macro.Set("PAD_CFG_GPIO_BIDIRECT")
if ios {
@@ -373,19 +367,15 @@
macro.Own().Add("),")
}
-const (
- rxDisable uint8 = 0x2
- txDisable uint8 = 0x1
-)
-
// Gets base string of current macro
// return: string of macro
func (macro *Macro) Generate() string {
- dw0 := macro.Register(PAD_CFG_DW0)
+ const rxDisable uint32 = 0x2
+ const txDisable uint32 = 0x1
macro.Platform.RemmapRstSrc()
macro.Set("PAD_CFG")
- if dw0.GetPadMode() == 0 {
+ if dw0 := macro.GetRegisterDW0(); dw0.GetPadMode() == 0 {
// GPIO
switch dw0.GetGPIORxTxDisableStatus() {
case txDisable:
@@ -414,7 +404,9 @@
if !config.AutoCheck {
body := macro.Get()
if config.GenLevel >= 3 {
- macro.Clear().DecodeIgnored(PAD_CFG_DW0).DecodeIgnored(PAD_CFG_DW1)
+ macro.Clear()
+ macro.DecodeIgnoredFieldsDW0()
+ macro.DecodeIgnoredFieldsDW1()
comment := macro.Get()
if config.GenLevel >= 4 {
macro.Clear().Add("/* ")
diff --git a/util/intelp2m/platforms/common/register.go b/util/intelp2m/platforms/common/register.go
deleted file mode 100644
index 2aa51b9..0000000
--- a/util/intelp2m/platforms/common/register.go
+++ /dev/null
@@ -1,262 +0,0 @@
-package common
-
-// Bit field constants for PAD_CFG_DW0 register
-const (
- AllFields uint32 = 0xffffffff
-
- PadRstCfgShift uint8 = 30
- PadRstCfgMask uint32 = 0x3 << PadRstCfgShift
-
- RxPadStateSelectShift uint8 = 29
- RxPadStateSelectMask uint32 = 0x1 << RxPadStateSelectShift
-
- RxRawOverrideTo1Shift uint8 = 28
- RxRawOverrideTo1Mask uint32 = 0x1 << RxRawOverrideTo1Shift
-
- RxLevelEdgeConfigurationShift uint8 = 25
- RxLevelEdgeConfigurationMask uint32 = 0x3 << RxLevelEdgeConfigurationShift
-
- RxInvertShift uint8 = 23
- RxInvertMask uint32 = 0x1 << RxInvertShift
-
- RxTxEnableConfigShift uint8 = 21
- RxTxEnableConfigMask uint32 = 0x3 << RxTxEnableConfigShift
-
- InputRouteIOxApicShift uint8 = 20
- InputRouteIOxApicMask uint32 = 0x1 << InputRouteIOxApicShift
-
- InputRouteSCIShift uint8 = 19
- InputRouteSCIMask uint32 = 0x1 << InputRouteSCIShift
-
- InputRouteSMIShift uint8 = 18
- InputRouteSMIMask uint32 = 0x1 << InputRouteSMIShift
-
- InputRouteNMIShift uint8 = 17
- InputRouteNMIMask uint32 = 0x1 << InputRouteNMIShift
-
- PadModeShift uint8 = 10
- PadModeMask uint32 = 0x7 << PadModeShift
-
- RxTxBufDisableShift uint8 = 8
- RxTxBufDisableMask uint32 = 0x3 << RxTxBufDisableShift
-
- RxStateShift uint8 = 1
- RxStateMask uint32 = 0x1 << RxStateShift
-
- TxStateMask uint32 = 0x1
-)
-
-// config DW registers
-const (
- PAD_CFG_DW0 = 0
- PAD_CFG_DW1 = 1
- MAX_DW_NUM = 2
-)
-
-// Register - configuration data structure based on DW0/1 dw value
-// value : register value
-// mask : bit fileds mask
-// roFileds : read only fields mask
-type Register struct {
- value uint32
- mask uint32
- roFileds uint32
-}
-
-func (reg *Register) ValueSet(value uint32) *Register {
- reg.value = value
- return reg
-}
-
-func (reg *Register) ValueGet() uint32 {
- return reg.value
-}
-
-func (reg *Register) ReadOnlyFieldsSet(fileldMask uint32) *Register {
- reg.roFileds = fileldMask
- return reg
-}
-
-func (reg *Register) ReadOnlyFieldsGet() uint32 {
- return reg.roFileds
-}
-
-// Check the mask of the new macro
-// Returns true if the macro is generated correctly
-func (reg *Register) MaskCheck() bool {
- mask := ^(reg.mask | reg.roFileds)
- return reg.value&mask == 0
-}
-
-// getResetConfig - get Reset Configuration from PADRSTCFG field in PAD_CFG_DW0_GPx register
-func (reg *Register) getFieldVal(mask uint32, shift uint8) uint8 {
- reg.mask |= mask
- return uint8((reg.value & mask) >> shift)
-}
-
-// CntrMaskFieldsClear - clear filed in control mask
-// fieldMask - mask of the field to be cleared
-func (reg *Register) CntrMaskFieldsClear(fieldMask uint32) {
- reg.mask &= ^fieldMask;
-}
-
-// IgnoredFieldsGet - return mask of unchecked (ignored) fields.
-// These bit fields were not read when the macro was
-// generated.
-// return
-// mask of ignored bit field
-func (reg *Register) IgnoredFieldsGet() uint32 {
- mask := reg.mask | reg.roFileds
- return reg.value & ^mask
-}
-
-// getResetConfig - returns type reset source for corresponding pad
-// PADRSTCFG field in PAD_CFG_DW0 register
-func (reg *Register) GetResetConfig() uint8 {
- return reg.getFieldVal(PadRstCfgMask, PadRstCfgShift)
-}
-
-// getRXPadStateSelect - returns RX Pad State (RXINV)
-// 0 = Raw RX pad state directly from RX buffer
-// 1 = Internal RX pad state
-func (reg *Register) GetRXPadStateSelect() uint8 {
- return reg.getFieldVal(RxPadStateSelectMask, RxPadStateSelectShift)
-}
-
-// getRXRawOverrideStatus - returns 1 if the selected pad state is being
-// overridden to '1' (RXRAW1 field)
-func (reg *Register) GetRXRawOverrideStatus() uint8 {
- return reg.getFieldVal(RxRawOverrideTo1Mask, RxRawOverrideTo1Shift)
-}
-
-// getRXLevelEdgeConfiguration - returns RX Level/Edge Configuration (RXEVCFG)
-// 0h = Level, 1h = Edge, 2h = Drive '0', 3h = Reserved (implement as setting 0h)
-func (reg *Register) GetRXLevelEdgeConfiguration() uint8 {
- return reg.getFieldVal(RxLevelEdgeConfigurationMask, RxLevelEdgeConfigurationShift)
-}
-
-// GetRxInvert - returns RX Invert state (RXINV)
-// 1 - Inversion, 0 - No inversion
-func (reg *Register) GetRxInvert() uint8 {
- return reg.getFieldVal(RxInvertMask, RxInvertShift)
-}
-
-// getRxTxEnableConfig - returns RX/TX Enable Config (RXTXENCFG)
-// 0 = Function defined in Pad Mode controls TX and RX Enables
-// 1 = Function controls TX Enable and RX Disabled with RX drive 0 internally
-// 2 = Function controls TX Enable and RX Disabled with RX drive 1 internally
-// 3 = Function controls TX Enabled and RX is always enabled
-func (reg *Register) GetRxTxEnableConfig() uint8 {
- return reg.getFieldVal(RxTxEnableConfigMask, RxTxEnableConfigShift)
-}
-
-// getGPIOInputRouteIOxAPIC - returns 1 if the pad can be routed to cause
-// peripheral IRQ when configured in GPIO input mode.
-func (reg *Register) GetGPIOInputRouteIOxAPIC() uint8 {
- return reg.getFieldVal(InputRouteIOxApicMask, InputRouteIOxApicShift)
-}
-
-// getGPIOInputRouteSCI - returns 1 if the pad can be routed to cause SCI when
-// configured in GPIO input mode.
-func (reg *Register) GetGPIOInputRouteSCI() uint8 {
- return reg.getFieldVal(InputRouteSCIMask, InputRouteSCIShift)
-}
-
-// getGPIOInputRouteSMI - returns 1 if the pad can be routed to cause SMI when
-// configured in GPIO input mode
-func (reg *Register) GetGPIOInputRouteSMI() uint8 {
- return reg.getFieldVal(InputRouteSMIMask, InputRouteSMIShift)
-}
-
-// getGPIOInputRouteNMI - returns 1 if the pad can be routed to cause NMI when
-// configured in GPIO input mode
-func (reg *Register) GetGPIOInputRouteNMI() uint8 {
- return reg.getFieldVal(InputRouteNMIMask, InputRouteNMIShift)
-}
-
-// getPadMode - reutrns pad mode or one of the native functions
-// 0h = GPIO control the Pad.
-// 1h = native function 1, if applicable, controls the Pad
-// 2h = native function 2, if applicable, controls the Pad
-// 3h = native function 3, if applicable, controls the Pad
-// 4h = enable GPIO blink/PWM capability if applicable
-func (reg *Register) GetPadMode() uint8 {
- return reg.getFieldVal(PadModeMask, PadModeShift)
-}
-
-// getGPIORxTxDisableStatus - returns GPIO RX/TX buffer state (GPIORXDIS | GPIOTXDIS)
-// 0 - both are enabled, 1 - TX Disable, 2 - RX Disable, 3 - both are disabled
-func (reg *Register) GetGPIORxTxDisableStatus() uint8 {
- return reg.getFieldVal(RxTxBufDisableMask, RxTxBufDisableShift)
-}
-
-// getGPIORXState - returns GPIO RX State (GPIORXSTATE)
-func (reg *Register) GetGPIORXState() uint8 {
- return reg.getFieldVal(RxStateMask, RxStateShift)
-}
-
-// getGPIOTXState - returns GPIO TX State (GPIOTXSTATE)
-func (reg *Register) GetGPIOTXState() uint8 {
- return reg.getFieldVal(TxStateMask, 0)
-}
-
-// Bit field constants for PAD_CFG_DW1 register
-const (
- PadTolShift uint8 = 25
- PadTolMask uint32 = 0x1 << PadTolShift
-
- IOStandbyStateShift uint8 = 14
- IOStandbyStateMask uint32 = 0xF << IOStandbyStateShift
-
- TermShift uint8 = 10
- TermMask uint32 = 0xF << TermShift
-
- IOStandbyTerminationShift uint8 = 8
- IOStandbyTerminationMask uint32 = 0x3 << IOStandbyTerminationShift
-
- InterruptSelectMask uint32 = 0xFF
-)
-
-// GetPadTol
-func (reg *Register) GetPadTol() uint8 {
- return reg.getFieldVal(PadTolMask, PadTolShift)
-}
-
-// getIOStandbyState - return IO Standby State (IOSSTATE)
-// 0 = Tx enabled driving last value driven, Rx enabled
-// 1 = Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller internally
-// 2 = Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller internally
-// 3 = Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller internally
-// 4 = Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller internally
-// 5 = Tx enabled driving 0, Rx enabled
-// 6 = Tx enabled driving 1, Rx enabled
-// 7 = Hi-Z, Rx driving 0 back to its controller internally
-// 8 = Hi-Z, Rx driving 1 back to its controller internally
-// 9 = Tx disabled, Rx enabled
-// 15 = IO-Standby is ignored for this pin (same as functional mode)
-// Others reserved
-func (reg *Register) GetIOStandbyState() uint8 {
- return reg.getFieldVal(IOStandbyStateMask, IOStandbyStateShift)
-}
-
-// getIOStandbyTermination - return IO Standby Termination (IOSTERM)
-// 0 = Same as functional mode (no change)
-// 1 = Disable Pull-up and Pull-down (no on-die termination)
-// 2 = Enable Pull-down
-// 3 = Enable Pull-up
-func (reg *Register) GetIOStandbyTermination() uint8 {
- return reg.getFieldVal(IOStandbyTerminationMask, IOStandbyTerminationShift)
-}
-
-// getTermination - returns the pad termination state defines the different weak
-// pull-up and pull-down settings that are supported by the buffer
-// 0000 = none; 0010 = 5k PD; 0100 = 20k PD; 1010 = 5k PU; 1100 = 20k PU;
-// 1111 = Native controller selected
-func (reg *Register) GetTermination() uint8 {
- return reg.getFieldVal(TermMask, TermShift)
-}
-
-// getInterruptSelect - returns Interrupt Line number from the GPIO controller
-func (reg *Register) GetInterruptSelect() uint8 {
- return reg.getFieldVal(InterruptSelectMask, 0)
-}
diff --git a/util/intelp2m/platforms/common/register/bits/bits.go b/util/intelp2m/platforms/common/register/bits/bits.go
new file mode 100644
index 0000000..a156e20
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/bits/bits.go
@@ -0,0 +1,92 @@
+package bits
+
+type Offset uint8
+
+const All32 uint32 = 0b11111111111111111111111111111111
+
+const (
+ DW0PadRstCfg Offset = 30
+ DW0RxPadStateSelect Offset = 29
+ DW0RxRawOverrideTo1 Offset = 28
+ DW0RxLevelEdgeConfiguration Offset = 25
+ DW0RxInvert Offset = 23
+ DW0RxTxEnableConfig Offset = 21
+ DW0InputRouteIOxApic Offset = 20
+ DW0InputRouteSCI Offset = 19
+ DW0InputRouteSMI Offset = 18
+ DW0InputRouteNMI Offset = 17
+ DW0PadMode Offset = 10
+ DW0RxTxBufDisable Offset = 8
+ DW0RxState Offset = 1
+ DW0TxState Offset = 0
+)
+
+const (
+ RstCfgPWROK = 0b00
+ RstCfgDEEP = 0b01
+ RstCfgPLTRST = 0b10
+ RstCfgRSMRST = 0b11
+)
+
+const (
+ TrigLEVEL = 0b00
+ TrigEDGE_SINGLE = 0b01
+ TrigOFF = 0b10
+ TrigEDGE_BOTH = 0b11
+)
+
+type Fields map[Offset]uint32
+
+var DW0 = Fields{
+ DW0PadRstCfg: 0b11 << DW0PadRstCfg,
+ DW0RxPadStateSelect: 0b1 << DW0RxPadStateSelect,
+ DW0RxRawOverrideTo1: 0b1 << DW0RxRawOverrideTo1,
+ DW0RxLevelEdgeConfiguration: 0b11 << DW0RxLevelEdgeConfiguration,
+ DW0RxInvert: 0b1 << DW0RxInvert,
+ DW0RxTxEnableConfig: 0b11 << DW0RxTxEnableConfig,
+ DW0InputRouteIOxApic: 0b1 << DW0InputRouteIOxApic,
+ DW0InputRouteSCI: 0b1 << DW0InputRouteSCI,
+ DW0InputRouteSMI: 0b1 << DW0InputRouteSMI,
+ DW0InputRouteNMI: 0b1 << DW0InputRouteNMI,
+ DW0PadMode: 0b111 << DW0PadMode,
+ DW0RxTxBufDisable: 0b11 << DW0RxTxBufDisable,
+ DW0RxState: 0b1 << DW0RxState,
+ DW0TxState: 0b1 << DW0TxState,
+}
+
+const (
+ DW1PadTol Offset = 25
+ DW1IOStandbyState Offset = 14
+ DW1Term Offset = 10
+ DW1IOStandbyTermination Offset = 8
+ DW1InterruptSelect Offset = 0
+)
+
+const (
+ IOStateTxLASTRxE = 0b0000
+ IOStateTx0RxDCRx0 = 0b0001
+ IOStateTx0RxDCRx1 = 0b0010
+ IOStateTx1RxDCRx0 = 0b0011
+ IOStateTx1RxDCRx1 = 0b0100
+ IOStateTx0RxE = 0b0101
+ IOStateTx1RxE = 0b0110
+ IOStateHIZCRx0 = 0b0111
+ IOStateHIZCRx1 = 0b1000
+ IOStateTxDRxE = 0b1001
+ IOStateStandbyIgnore = 0b1111
+)
+
+const (
+ IOTermSAME = 0b00
+ IOTermDISPUPD = 0b01
+ IOTermENPD = 0b10
+ IOTermENPU = 0b11
+)
+
+var DW1 = Fields{
+ DW1PadTol: 0b1 << DW1PadTol,
+ DW1IOStandbyState: 0b1111 << DW1IOStandbyState,
+ DW1Term: 0b1111 << DW1Term,
+ DW1IOStandbyTermination: 0b11 << DW1IOStandbyTermination,
+ DW1InterruptSelect: 0b11111111 << DW1InterruptSelect,
+}
diff --git a/util/intelp2m/platforms/common/register/dw0.go b/util/intelp2m/platforms/common/register/dw0.go
new file mode 100644
index 0000000..4c264c3
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/dw0.go
@@ -0,0 +1,101 @@
+package register
+
+import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
+
+type DW0 struct {
+ Register
+}
+
+func (dw0 DW0) GetBitfield() bits.Fields {
+ return bits.DW0
+}
+
+// getResetConfig - returns type reset source for corresponding pad
+// PADRSTCFG field in PAD_CFG_DW0 register
+func (dw0 *DW0) GetResetConfig() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0PadRstCfg)
+}
+
+// getRXPadStateSelect - returns RX Pad State (RXINV)
+// 0 = Raw RX pad state directly from RX buffer
+// 1 = Internal RX pad state
+func (dw0 *DW0) GetRXPadStateSelect() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0RxPadStateSelect)
+}
+
+// getRXRawOverrideStatus - returns 1 if the selected pad state is being
+// overridden to '1' (RXRAW1 field)
+func (dw0 *DW0) GetRXRawOverrideStatus() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0RxRawOverrideTo1)
+}
+
+// getRXLevelEdgeConfiguration - returns RX Level/Edge Configuration (RXEVCFG)
+// 0h = Level, 1h = Edge, 2h = Drive '0', 3h = Reserved (implement as setting 0h)
+func (dw0 *DW0) GetRXLevelEdgeConfiguration() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0RxLevelEdgeConfiguration)
+}
+
+// GetRxInvert - returns RX Invert state (RXINV)
+// 1 - Inversion, 0 - No inversion
+func (dw0 *DW0) GetRxInvert() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0RxInvert)
+}
+
+// getRxTxEnableConfig - returns RX/TX Enable Config (RXTXENCFG)
+// 0 = Function defined in Pad Mode controls TX and RX Enables
+// 1 = Function controls TX Enable and RX Disabled with RX drive 0 internally
+// 2 = Function controls TX Enable and RX Disabled with RX drive 1 internally
+// 3 = Function controls TX Enabled and RX is always enabled
+func (dw0 *DW0) GetRxTxEnableConfig() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0RxTxEnableConfig)
+}
+
+// getGPIOInputRouteIOxAPIC - returns 1 if the pad can be routed to cause
+// peripheral IRQ when configured in GPIO input mode.
+func (dw0 *DW0) GetGPIOInputRouteIOxAPIC() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteIOxApic)
+}
+
+// getGPIOInputRouteSCI - returns 1 if the pad can be routed to cause SCI when
+// configured in GPIO input mode.
+func (dw0 *DW0) GetGPIOInputRouteSCI() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteSCI)
+}
+
+// getGPIOInputRouteSMI - returns 1 if the pad can be routed to cause SMI when
+// configured in GPIO input mode
+func (dw0 *DW0) GetGPIOInputRouteSMI() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteSMI)
+}
+
+// getGPIOInputRouteNMI - returns 1 if the pad can be routed to cause NMI when
+// configured in GPIO input mode
+func (dw0 *DW0) GetGPIOInputRouteNMI() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0InputRouteNMI)
+}
+
+// getPadMode - reutrns pad mode or one of the native functions
+// 0h = GPIO control the Pad.
+// 1h = native function 1, if applicable, controls the Pad
+// 2h = native function 2, if applicable, controls the Pad
+// 3h = native function 3, if applicable, controls the Pad
+// 4h = enable GPIO blink/PWM capability if applicable
+func (dw0 *DW0) GetPadMode() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0PadMode)
+}
+
+// getGPIORxTxDisableStatus - returns GPIO RX/TX buffer state (GPIORXDIS | GPIOTXDIS)
+// 0 - both are enabled, 1 - TX Disable, 2 - RX Disable, 3 - both are disabled
+func (dw0 *DW0) GetGPIORxTxDisableStatus() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0RxTxBufDisable)
+}
+
+// getGPIORXState - returns GPIO RX State (GPIORXSTATE)
+func (dw0 *DW0) GetGPIORXState() uint32 {
+ return dw0.GetFieldVal(bits.DW0, bits.DW0RxState)
+}
+
+// getGPIOTXState - returns GPIO TX State (GPIOTXSTATE)
+func (dw0 *DW0) GetGPIOTXState() uint32 {
+ return dw0.GetFieldVal(bits.DW0, 0)
+}
diff --git a/util/intelp2m/platforms/common/register/dw1.go b/util/intelp2m/platforms/common/register/dw1.go
new file mode 100644
index 0000000..d59adef
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/dw1.go
@@ -0,0 +1,51 @@
+package register
+
+import "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
+
+type DW1 struct {
+ Register
+}
+
+// GetPadTol
+func (dw1 *DW1) GetPadTol() uint32 {
+ return dw1.GetFieldVal(bits.DW1, bits.DW1PadTol)
+}
+
+// GetIOStandbyState() return IO Standby State (IOSSTATE)
+// 0 = Tx enabled driving last value driven, Rx enabled
+// 1 = Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller internally
+// 2 = Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller internally
+// 3 = Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller internally
+// 4 = Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller internally
+// 5 = Tx enabled driving 0, Rx enabled
+// 6 = Tx enabled driving 1, Rx enabled
+// 7 = Hi-Z, Rx driving 0 back to its controller internally
+// 8 = Hi-Z, Rx driving 1 back to its controller internally
+// 9 = Tx disabled, Rx enabled
+// 15 = IO-Standby is ignored for this pin (same as functional mode)
+// Others reserved
+func (dw1 *DW1) GetIOStandbyState() uint32 {
+ return dw1.GetFieldVal(bits.DW1, bits.DW1IOStandbyState)
+}
+
+// GetIOStandbyTermination() return IO Standby Termination (IOSTERM)
+// 0 = Same as functional mode (no change)
+// 1 = Disable Pull-up and Pull-down (no on-die termination)
+// 2 = Enable Pull-down
+// 3 = Enable Pull-up
+func (dw1 *DW1) GetIOStandbyTermination() uint32 {
+ return dw1.GetFieldVal(bits.DW1, bits.DW1IOStandbyTermination)
+}
+
+// GetTermination() returns the pad termination state defines the different weak
+// pull-up and pull-down settings that are supported by the buffer
+// 0000 = none; 0010 = 5k PD; 0100 = 20k PD; 1010 = 5k PU; 1100 = 20k PU;
+// 1111 = Native controller selected
+func (dw1 *DW1) GetTermination() uint32 {
+ return dw1.GetFieldVal(bits.DW1, bits.DW1Term)
+}
+
+// GetInterruptSelect() returns Interrupt Line number from the GPIO controller
+func (dw1 *DW1) GetInterruptSelect() uint32 {
+ return dw1.GetFieldVal(bits.DW1, bits.DW1InterruptSelect)
+}
diff --git a/util/intelp2m/platforms/common/register/register.go b/util/intelp2m/platforms/common/register/register.go
new file mode 100644
index 0000000..76fd9d1
--- /dev/null
+++ b/util/intelp2m/platforms/common/register/register.go
@@ -0,0 +1,46 @@
+package register
+
+import (
+ "fmt"
+
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
+)
+
+type Register struct {
+ Value uint32
+ Mask uint32
+ ReadOnly uint32
+}
+
+// Check the mask of the new macro
+// Returns true if the macro is generated correctly
+func (r Register) MaskCheck() bool {
+ mask := ^(r.Mask | r.ReadOnly)
+ return (r.Value & mask) == 0
+}
+
+// GetFieldVal() gets the value of the register bit field
+func (r *Register) GetFieldVal(bitfields bits.Fields, offset bits.Offset) uint32 {
+ mask := bitfields[offset]
+ r.Mask |= mask
+ return (r.Value & mask) >> offset
+}
+
+// CntrMaskFieldsClear() clear filed in control mask
+// fieldMask - mask of the field to be cleared
+func (r *Register) CntrMaskFieldsClear(fieldMask uint32) {
+ r.Mask &= ^fieldMask
+}
+
+// IgnoredFieldsGet() returns mask of unchecked (ignored) fields.
+// These bit fields were not read when the macro was generated.
+// return
+// mask of ignored bit field
+func (r Register) IgnoredFieldsGet() uint32 {
+ mask := r.Mask | r.ReadOnly
+ return r.Value & ^mask
+}
+
+func (r Register) String() string {
+ return fmt.Sprintf("0x%0.8x", r.Value)
+}
diff --git a/util/intelp2m/platforms/lbg/macro.go b/util/intelp2m/platforms/lbg/macro.go
index bb08e28..63b7d2b 100644
--- a/util/intelp2m/platforms/lbg/macro.go
+++ b/util/intelp2m/platforms/lbg/macro.go
@@ -5,6 +5,7 @@
"review.coreboot.org/coreboot.git/util/intelp2m/fields"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr"
)
@@ -13,12 +14,6 @@
PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
)
-const (
- PAD_CFG_DW0 = common.PAD_CFG_DW0
- PAD_CFG_DW1 = common.PAD_CFG_DW1
- MAX_DW_NUM = common.MAX_DW_NUM
-)
-
type InheritanceMacro interface {
Pull()
GpiMacroAdd()
@@ -35,21 +30,22 @@
// RemmapRstSrc - remmap Pad Reset Source Config
func (PlatformSpecific) RemmapRstSrc() {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- var remapping = map[uint8]uint32{
- 0: common.RST_RSMRST << common.PadRstCfgShift,
- 1: common.RST_DEEP << common.PadRstCfgShift,
- 2: common.RST_PLTRST << common.PadRstCfgShift,
+ dw0 := macro.GetRegisterDW0()
+ remapping := map[uint32]uint32{
+ 0: (bits.RstCfgRSMRST << bits.DW0PadRstCfg),
+ 1: (bits.RstCfgDEEP << bits.DW0PadRstCfg),
+ 2: (bits.RstCfgPLTRST << bits.DW0PadRstCfg),
}
resetsrc, valid := remapping[dw0.GetResetConfig()]
if valid {
// dw0.SetResetConfig(resetsrc)
- ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
- dw0.ValueSet(ResetConfigFieldVal)
+ ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+ dw0.Value = ResetConfigFieldVal
} else {
fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
}
- dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+ mask := bits.DW0[bits.DW0PadRstCfg]
+ dw0.CntrMaskFieldsClear(mask)
}
// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
@@ -79,20 +75,27 @@
}
// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0val : DW0 config register value
+// dw1val : DW1 config register value
// return: string of macro
// error
-func (platform PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (platform PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
// The GPIO controller architecture in Lewisburg and Sunrise are very similar,
// so we will inherit some platform-dependent functions from Sunrise.
macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}},
fields.InterfaceGet())
macro.Clear()
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+ dw0 := macro.GetRegisterDW0()
+ dw0.CntrMaskFieldsClear(bits.All32)
+
+ dw1 := macro.GetRegisterDW1()
+ dw1.CntrMaskFieldsClear(bits.All32)
+
+ dw0.Value = dw0Val
+ dw1.Value = dw1Val
+
+ dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+ dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
macro.PadIdSet(id).SetPadOwnership(ownership)
- macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
- macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
return macro.Generate()
}
diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go
index 5ead7e9..f1d05e7 100644
--- a/util/intelp2m/platforms/snr/macro.go
+++ b/util/intelp2m/platforms/snr/macro.go
@@ -7,6 +7,7 @@
"review.coreboot.org/coreboot.git/util/intelp2m/config/p2m"
"review.coreboot.org/coreboot.git/util/intelp2m/fields"
"review.coreboot.org/coreboot.git/util/intelp2m/platforms/common"
+ "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common/register/bits"
)
const (
@@ -14,12 +15,6 @@
PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff
)
-const (
- PAD_CFG_DW0 = common.PAD_CFG_DW0
- PAD_CFG_DW1 = common.PAD_CFG_DW1
- MAX_DW_NUM = common.MAX_DW_NUM
-)
-
type PlatformSpecific struct{}
// RemmapRstSrc - remmap Pad Reset Source Config
@@ -32,29 +27,30 @@
return
}
- dw0 := macro.Register(PAD_CFG_DW0)
- var remapping = map[uint8]uint32{
- 0: common.RST_RSMRST << common.PadRstCfgShift,
- 1: common.RST_DEEP << common.PadRstCfgShift,
- 2: common.RST_PLTRST << common.PadRstCfgShift,
+ dw0 := macro.GetRegisterDW0()
+ remapping := map[uint32]uint32{
+ 0: bits.RstCfgRSMRST << bits.DW0PadRstCfg,
+ 1: bits.RstCfgDEEP << bits.DW0PadRstCfg,
+ 2: bits.RstCfgPLTRST << bits.DW0PadRstCfg,
}
resetsrc, valid := remapping[dw0.GetResetConfig()]
if valid {
// dw0.SetResetConfig(resetsrc)
- ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()]
- dw0.ValueSet(ResetConfigFieldVal)
+ ResetConfigFieldVal := (dw0.Value & 0x3fffffff) | remapping[dw0.GetResetConfig()]
+ dw0.Value = ResetConfigFieldVal
} else {
fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc, " ] for ", macro.PadIdGet())
}
- dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+ mask := bits.DW0[bits.DW0PadRstCfg]
+ dw0.CntrMaskFieldsClear(mask)
}
// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro
// as a new argument
func (PlatformSpecific) Pull() {
macro := common.GetMacro()
- dw1 := macro.Register(PAD_CFG_DW1)
- var pull = map[uint8]string{
+ dw1 := macro.GetRegisterDW1()
+ var pull = map[uint32]string{
0x0: "NONE",
0x2: "DN_5K",
0x4: "DN_20K",
@@ -79,13 +75,13 @@
// Generate macro to cause peripheral IRQ when configured in GPIO input mode
func ioApicRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
if dw0.GetGPIOInputRouteIOxAPIC() == 0 {
return false
}
macro.Add("_APIC")
- if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL {
+ if dw0.GetRXLevelEdgeConfiguration() == bits.TrigLEVEL {
if dw0.GetRxInvert() != 0 {
// PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
macro.Add("_LOW")
@@ -105,7 +101,7 @@
// Generate macro to cause NMI when configured in GPIO input mode
func nmiRoute() bool {
macro := common.GetMacro()
- if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 {
+ if macro.GetRegisterDW0().GetGPIOInputRouteNMI() == 0 {
return false
}
// PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
@@ -116,7 +112,7 @@
// Generate macro to cause SCI when configured in GPIO input mode
func sciRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
if dw0.GetGPIOInputRouteSCI() == 0 {
return false
}
@@ -128,7 +124,7 @@
// Generate macro to cause SMI when configured in GPIO input mode
func smiRoute() bool {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
if dw0.GetGPIOInputRouteSMI() == 0 {
return false
}
@@ -175,23 +171,24 @@
default:
// Clear the control mask so that the check fails and "Advanced" macro is
// generated
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+ macro.GetRegisterDW0().CntrMaskFieldsClear(bits.All32)
}
}
// Adds PAD_CFG_GPO macro with arguments
func (PlatformSpecific) GpoMacroAdd() {
macro := common.GetMacro()
- dw0 := macro.Register(PAD_CFG_DW0)
- term := macro.Register(PAD_CFG_DW1).GetTermination()
+ dw0 := macro.GetRegisterDW0()
+ term := macro.GetRegisterDW1().GetTermination()
// #define PAD_CFG_GPO(pad, val, rst) \
// _PAD_CFG_STRUCT(pad, \
// PAD_FUNC(GPIO) | PAD_RESET(rst) | \
// PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
// PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
- if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
- dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+ if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+ mask := bits.DW0[bits.DW0RxLevelEdgeConfiguration]
+ dw0.CntrMaskFieldsClear(mask)
}
macro.Set("PAD_CFG")
if macro.IsOwnershipDriver() {
@@ -215,7 +212,7 @@
macro := common.GetMacro()
// e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1)
macro.Set("PAD_CFG_NF")
- if macro.Register(PAD_CFG_DW1).GetPadTol() != 0 {
+ if macro.GetRegisterDW1().GetPadTol() != 0 {
macro.Add("_1V8")
}
macro.Add("(").Id().Pull().Rstsrc().Padfn().Add("),")
@@ -228,32 +225,41 @@
// _PAD_CFG_STRUCT(pad,
// PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
// PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)),
- dw0 := macro.Register(PAD_CFG_DW0)
+ dw0 := macro.GetRegisterDW0()
// Some fields of the configuration registers are hidden inside the macros,
// we should check them to update the corresponding bits in the control mask.
- if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF {
- dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask)
+ if dw0.GetRXLevelEdgeConfiguration() != bits.TrigOFF {
+ mask := bits.DW0[bits.DW0RxLevelEdgeConfiguration]
+ dw0.CntrMaskFieldsClear(mask)
}
if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP
- dw0.CntrMaskFieldsClear(common.PadRstCfgMask)
+ mask := bits.DW0[bits.DW0PadRstCfg]
+ dw0.CntrMaskFieldsClear(mask)
}
macro.Set("PAD_NC").Add("(").Id().Pull().Add("),")
}
// GenMacro - generate pad macro
-// dw0 : DW0 config register value
-// dw1 : DW1 config register value
+// dw0Val : DW0 config register value
+// dw1Val : DW1 config register value
// return: string of macro
// error
-func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string {
+func (PlatformSpecific) GenMacro(id string, dw0Val uint32, dw1Val uint32, ownership uint8) string {
macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet())
macro.Clear()
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
- macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields)
+ dw0 := macro.GetRegisterDW0()
+ dw0.CntrMaskFieldsClear(bits.All32)
+
+ dw1 := macro.GetRegisterDW1()
+ dw1.CntrMaskFieldsClear(bits.All32)
+
+ dw0.Value = dw0Val
+ dw1.Value = dw1Val
+
+ dw0.ReadOnly = PAD_CFG_DW0_RO_FIELDS
+ dw1.ReadOnly = PAD_CFG_DW1_RO_FIELDS
macro.PadIdSet(id).SetPadOwnership(ownership)
- macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS)
- macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS)
return macro.Generate()
}
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