Kyösti Mälkki would like Marshall Dawson to review this change.

View Change

[WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs

The memory between _car_region_start .. _car_region_end has to
be set up as WB in MTRRs for all the cores executing through
bootblock, verstage and romstage. Otherwise CAR_GLOBALs may
fail on AP CPUs.

Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n,
which previously did not boot at all.

Does not fix family14.

Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
M src/vendorcode/amd/agesa/f12/gcccar.inc
M src/vendorcode/amd/agesa/f14/gcccar.inc
M src/vendorcode/amd/agesa/f15tn/gcccar.inc
M src/vendorcode/amd/agesa/f16kb/gcccar.inc
4 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31361/1

diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index 95dd74d..e6dba6a 100644
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -1451,6 +1451,13 @@
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 95dd74d..e6dba6a 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -1451,6 +1451,13 @@
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index b13e02a..e96c7f7 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1767,6 +1767,13 @@
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index c818d97..26745c9 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -1131,6 +1131,13 @@
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR

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