Arthur Heymans uploaded patch set #36 to this change.

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soc/intel/fsp1.1: Implement postcar stage

This moves FSP1.1 to use postcar stage to tear down CAR.
On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found
during the postcar stage so there is no need to push to save it
in CAR global variables.

On FSP1.1 platforms with an open source CAR implementation (Skylake,
even though it still runs the FSP-T), the
soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR.

This also uses common functions to set up the MTRR to use after
CAR is torn down.

Tested on Google/cyan (celes variant).
TOTEST: skylake with fsp1.1

Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/drivers/intel/fsp1_1/Kconfig
M src/drivers/intel/fsp1_1/Makefile.inc
D src/drivers/intel/fsp1_1/after_raminit.S
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/car.c
A src/drivers/intel/fsp1_1/exit_car.S
M src/drivers/intel/fsp1_1/include/fsp/car.h
M src/drivers/intel/fsp1_1/include/fsp/romstage.h
M src/drivers/intel/fsp1_1/include/fsp/util.h
M src/drivers/intel/fsp1_1/romstage.c
D src/drivers/intel/fsp1_1/stack.c
A src/drivers/intel/fsp1_1/temp_ram_exit.c
M src/soc/intel/braswell/Makefile.inc
M src/soc/intel/quark/include/soc/romstage.h
M src/soc/intel/quark/romstage/car_stage_entry.S
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/skylake/romstage/car_stage.S
17 files changed, 186 insertions(+), 410 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30686/36

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