Attention is currently required from: Benjamin Doron.

Benjamin Doron uploaded patch set #5 to this change.

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arch/x86/mmu: Port armv8 MMU to x86_64

Add functions to set up page tables for long mode.
In addition generate new page tables where necessary:
- before CBMEM setup, if CBMEM is above 4GiB
- after CBMEM setup, if CBMEM is above 4GiB
- at end of BS_DEV_RESOURCES in CBMEM

At end of BS_DEV_RESOURCES the memory map is fully known and the
page tables can be properly generated based on the memory resources.

This allows the CPU to access all DRAM and MMIO even beyond 4GiB.

Right now there's no use case for this, but the code is necessary to:
- Load stages above 4GiB
- Load payloads above 4GiB
- Install tables (like CBMEM/ACPI/SMBIOS) above 4GiB
- allow coreboot PCI drivers to access BARs mapped above 4GiB

Tested on prodrive/hermes: Still boots to payload.
Doesn't affect existing x86_32 code.

Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Co-authored-by: Benjamin Doron <benjamin.doron@9elements.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/Makefile.inc
A src/arch/x86/include/arch/mmu.h
A src/arch/x86/mmu-ramstage.c
A src/arch/x86/mmu-romstage.c
A src/arch/x86/mmu.c
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/lib/imd_cbmem.c
8 files changed, 631 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79161/5

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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992
Gerrit-Change-Number: 79161
Gerrit-PatchSet: 5
Gerrit-Owner: Benjamin Doron <benjamin.doron00@gmail.com>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-Attention: Benjamin Doron <benjamin.doron00@gmail.com>
Gerrit-MessageType: newpatchset