Patch Set 7: Code-Review+2

Patch Set 7:

All the actual Volteer variants will have CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) enabled, and in that case, it is obvious to see that this CL is a no-op.

Only the reworked Volteer prototypes, hooked up with external Dauntless development board, will use I2C instead of SPI for TPM communication, and could be affected by the logic change here.

Furquan, could you please +2 this.

I didn't +2 since I'm not a Googler, but I'm fine with this change.

Uh, I didn't explain myself very well. Since I'm not actively keeping track of Google development in coreboot, I usually don't know if changes to Google-specific code are OK or not, so I wait for a Googler to ack the idea before giving out a +2. However, given that this change is well-reasoned, I feel confident enough to +2 it.

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