Richard Spiegel has uploaded this change for review.
soc/amd/stoneyridge/lpc.c: Fix LPC host control
2 bits of LPC host control were originally not public, and wrongly
identified as IMC related. Now that the bits are available in public BKDG,
fix the naming of the bits.
BUG=b:111912080
TEST=build and boot grunt.
Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/lpc.c
2 files changed, 5 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27744/1
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index ece78b6..15c9581 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -213,8 +213,8 @@
#define SPI_FROM_USB_PREFETCH_EN BIT(23)
#define LPC_HOST_CONTROL 0xbb
-#define IMC_PAGE_FROM_HOST_EN BIT(0)
-#define IMC_PORT_FROM_HOST_EN BIT(3)
+#define PREFETCH_EN_SPI_FROM_HOST BIT(0)
+#define T_START_ENH BIT(3)
/* SPI Controller */
#define SPI_CNTRL0 0x00
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 4bf5a4f..6833db6 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -76,12 +76,11 @@
pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
/*
- * IMC is not used, but some of its registers and ports need to be
- * programmed/accessed. So enable CPU access to them. This fixes
- * SPI_CS# timing issue when running at 66MHz.
+ * Enable hand-instance of the pulse generator and SPI
+ * controller prefetch of flash.
*/
byte = pci_read_config8(dev, LPC_HOST_CONTROL);
- byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN;
+ byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH;
pci_write_config8(dev, LPC_HOST_CONTROL, byte);
cmos_check_update_date();
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