Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4502
-gerrit
commit 7de06d131e3899ba4f8307de86e28296661b622b Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sun Dec 8 07:21:05 2013 +0200
cpu/amd (non-AGESA): Load microcode updates from CBFS
Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/amd/microcode/microcode.c | 41 +++++++++++++++++----- src/cpu/amd/model_10xxx/Makefile.inc | 2 ++ src/cpu/amd/model_10xxx/microcode_blob.c | 28 +++++++++++++++ src/cpu/amd/model_10xxx/update_microcode.c | 27 ++------------ src/cpu/amd/model_fxx/Makefile.inc | 2 ++ src/cpu/amd/model_fxx/microcode_blob.c | 34 ++++++++++++++++++ src/cpu/amd/model_fxx/model_fxx_init.c | 2 +- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 30 +++------------- src/include/cpu/amd/microcode.h | 8 ++--- 9 files changed, 108 insertions(+), 66 deletions(-)
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index cdc6e4a..c9e2dcf 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/amd/microcode.h> +#include <cbfs.h>
struct microcode { u32 date_code; @@ -51,18 +52,13 @@ struct microcode { u8 x86_code_entry[191]; };
-void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_id) +static void amd_update_microcode(const void *microcode_updates, u32 microcode_len, u32 equivalent_processor_rev_id) { - u32 patch_id, new_patch_id; - struct microcode *m; - char *c; + u32 new_patch_id; + const struct microcode *m; + const char *c; msr_t msr;
- msr = rdmsr(0x8b); - patch_id = msr.lo; - - printk(BIOS_DEBUG, "microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id); - m = microcode_updates;
for(c = microcode_updates; m->date_code; m = (struct microcode *)c) { @@ -88,3 +84,30 @@ void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_ }
} + +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" + +void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id) +{ + struct cbfs_file *microcode_file; + const void *microcode_updates; + u32 microcode_len, patch_id; + msr_t msr; + + msr = rdmsr(0x8b); + patch_id = msr.lo; + + printk(BIOS_DEBUG, "microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id); + if (equivalent_processor_rev_id == 0) { + printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n"); + return; + } + + microcode_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, MICROCODE_CBFS_FILE); + if (!microcode_file) + return; + + microcode_updates = CBFS_SUBHEADER(microcode_file); + microcode_len = ntohl(microcode_file->len); + amd_update_microcode(microcode_updates, microcode_len, equivalent_processor_rev_id); +} diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index c82a26e..f7c0727 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,3 +3,5 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c
romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/amd/model_10xxx/microcode_blob.c b/src/cpu/amd/model_10xxx/microcode_blob.c new file mode 100644 index 0000000..c697cea --- /dev/null +++ b/src/cpu/amd/model_10xxx/microcode_blob.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned char microcode[] __attribute__ ((aligned(16))) = { +#include CONFIG_AMD_UCODE_PATCH_FILE + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index 95624e9..ebb8199 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -18,13 +18,8 @@ */
#include <stdint.h> -#include <console/console.h> #include <cpu/amd/microcode.h>
-static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { - -#ifdef __PRE_RAM__ - /* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors * @@ -46,16 +41,6 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100FA0h (PH-E0) 10A0h 010000bfh */
-#include CONFIG_AMD_UCODE_PATCH_FILE - -#endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static u32 get_equivalent_processor_rev_id(u32 orig_id) { static unsigned id_mapping_table[] = { 0x100f00, 0x1000, @@ -92,14 +77,6 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
void update_microcode(u32 cpu_deviceid) { - u32 equivalent_processor_rev_id; - - /* Update the microcode */ - equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); - if (equivalent_processor_rev_id != 0) { - amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id); - } else { - printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n"); - } - + u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid); + amd_update_microcode_from_cbfs(equivalent_processor_rev_id); } diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index eb62640..8730f41 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += model_fxx_init.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c new file mode 100644 index 0000000..3210f62 --- /dev/null +++ b/src/cpu/amd/model_fxx/microcode_blob.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned char microcode[] __attribute__ ((aligned(16))) = { +#if !CONFIG_K8_REV_F_SUPPORT + #include "microcode_rev_c.h" + #include "microcode_rev_d.h" + #include "microcode_rev_e.h" +#endif + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 260e83e..33226d4 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -468,7 +468,7 @@ static void model_fxx_init(device_t dev) x86_mtrr_check();
/* Update the microcode */ - model_fxx_update_microcode(dev->device); + update_microcode(dev->device);
disable_cache();
diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 4a53fea..ad22a05 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -19,27 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> +#include <stdint.h> #include <cpu/amd/microcode.h>
-static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { - -#if !CONFIG_K8_REV_F_SUPPORT - #include "microcode_rev_c.h" - #include "microcode_rev_d.h" - #include "microcode_rev_e.h" -#endif - -#if CONFIG_K8_REV_F_SUPPORT -// #include "microcode_rev_f.h" -#endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { #if !CONFIG_K8_REV_F_SUPPORT @@ -86,12 +68,8 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { return new_id; }
-void model_fxx_update_microcode(unsigned cpu_deviceid) +void update_microcode(u32 cpu_deviceid) { - unsigned equivalent_processor_rev_id; - - /* Update the microcode */ - equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); - if(equivalent_processor_rev_id != 0) - amd_update_microcode(microcode_updates, equivalent_processor_rev_id); + u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid); + amd_update_microcode_from_cbfs(equivalent_processor_rev_id); } diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index e6d686c..9876a24 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -1,11 +1,9 @@ #ifndef CPU_AMD_MICROCODE_H #define CPU_AMD_MICROCODE_H
-void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); -void model_fxx_update_microcode(unsigned cpu_deviceid); - -#if CONFIG_UPDATE_CPU_MICROCODE -void update_microcode(u32 processor_rev_id); +#if CONFIG_UPDATE_CPU_MICROCODE || CONFIG_NORTHBRIDGE_AMD_AMDK8 +void update_microcode(u32 cpu_deviceid); +void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id); #else #define update_microcode(x) #endif