1 comment:
File src/mainboard/google/drallion/romstage.c:
Patch Set #6, Line 64: PchIshEnable
This is already set in soc/intel/cannonlake/fsp_params.c based on dev->enabled. So, the only change you really need here is:
dev->enabled = is_ish_device_enabled(); where dev would be the ISH device.
However, looking at the flow in SoC, it looks like mainboard_memory_init_params() is called after soc_memory_init_params() is called. You will have to fix the order there to ensure that the mainboard call happens before.
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