Arthur Heymans uploaded patch set #4 to this change.

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soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR

This adds a macro to find an available MTRR(s) to set up CAR.
This added complexity is not required on bootpaths without bootguard
but with bootguard MTRR's have already been set up by the ACM so
we need to figure out at runtime which ones are available.

Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 43 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37190/4

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d
Gerrit-Change-Number: 37190
Gerrit-PatchSet: 4
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Patrick Georgi <pgeorgi@google.com>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
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