Felix Singer has uploaded this change for review.

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sb/intel: Use boolean for pcie_hotplug_map attribute

Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
M src/southbridge/intel/bd82x6x/chip.h
M src/southbridge/intel/common/pciehp.c
M src/southbridge/intel/common/pciehp.h
M src/southbridge/intel/i82801ix/chip.h
M src/southbridge/intel/i82801jx/chip.h
5 files changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/79932/1

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 30c2675..66d5cb1 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,7 +65,7 @@
 
 	int docking_supported;
 
-	uint8_t pcie_hotplug_map[8];
+	bool pcie_hotplug_map[8];
 
 	/* Ports which can be routed to either EHCI or xHCI.  */
 	uint32_t xhci_switchable_ports;
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
index b549619..a9da488 100644
--- a/src/southbridge/intel/common/pciehp.c
+++ b/src/southbridge/intel/common/pciehp.c
@@ -7,7 +7,7 @@
 
 #include "pciehp.h"
 
-void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number)
+void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number)
 {
 	int port;
 	int have_hotplug = 0;
diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h
index b4e65c4..2434b5b 100644
--- a/src/southbridge/intel/common/pciehp.h
+++ b/src/southbridge/intel/common/pciehp.h
@@ -3,7 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
 #define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
 
-void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number);
+void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number);
 void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus);
 
 #endif
diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h
index ec7b977..d52a0c2 100644
--- a/src/southbridge/intel/i82801ix/chip.h
+++ b/src/southbridge/intel/i82801ix/chip.h
@@ -3,6 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
 enum {
@@ -73,7 +74,7 @@
 		uint8_t scale : 2;
 	} pcie_power_limits[6];
 
-	uint8_t pcie_hotplug_map[8];
+	bool pcie_hotplug_map[8];
 
 	/* Additional LPC IO decode ranges */
 	uint32_t gen1_dec;
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index ae31d4f..f12a67e 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -3,6 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
 enum {
@@ -59,7 +60,7 @@
 		uint8_t scale : 2;
 	} pcie_power_limits[6];
 
-	uint8_t pcie_hotplug_map[8];
+	bool pcie_hotplug_map[8];
 
 	/* Additional LPC IO decode ranges */
 	uint32_t gen1_dec;

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