Kyösti Mälkki has uploaded this change for review.
[WIP] amd/stoneyridge: Fix CAR stack location
As far as I can see, for BSP, gcccar.inc exits with
%esp at _car_region_end, not _car_stack_end.
On exit from ENABLE_AMD_STACK, %esp will have value
of DCACHE_RAM_BASE + DCACHE_RAM_SIZE. This was correct
for the stack placement with C_ENVIRONMENT_BOOTBLOCK=n.
It would be nice if AMD code had guards so we knew how
much stack it needs. Setting of DCACHE_BSP_STACK_SIZE
works with inverse logic now, the higher you set it,
the less space is where the stack is located. This
raises the question how its size was determined.
00030000 B _car_region_start
00030000 B _car_stack_start
00034000 B _car_stack_end
00034000 B _preram_cbmem_console
00035600 B _car_relocatable_data_start
00035850 B _car_global_start
00035860 B _car_global_end
00035860 B _car_relocatable_data_end
00040000 B _car_region_end
Use the symbol _car_stack_end to have early stage use
the location assigned by the linker script car.ld.
Change-Id: Id91393f1e7faf86b01fdc113e7940893673a27a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M src/drivers/amd/agesa/cache_as_ram.S
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/34883/1
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 4f0bb3f..c23939c 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -31,6 +31,8 @@
.globl _cache_as_ram_setup, _cache_as_ram_setup_end
.globl chipset_teardown_car
+#if ENV_ROMSTAGE
+
_cache_as_ram_setup:
/* Preserve BIST. */
@@ -49,6 +51,10 @@
AMD_ENABLE_STACK
+ /* Let arch/x86/car.ld determine our stack location.
+ * FIXME: Only do this for BSP. !! */
+ movl $_car_stack_end, %esp
+
/* Align the stack. */
and $0xFFFFFFF0, %esp
@@ -107,6 +113,8 @@
pushl %eax
call romstage_main
+#endif /* ENV_ROMSTAGE */
+
#if CONFIG(POSTCAR_STAGE)
/* We do not return. Execution continues with run_postcar_phase()
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 402da3a..ad0ea53 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -38,6 +38,10 @@
AMD_ENABLE_STACK
+ /* Let arch/x86/car.ld determine our stack location.
+ * FIXME: Only do this for BSP. !! */
+ movl $_car_stack_end, %esp
+
/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp
sub $8, %esp
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