soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
---
M src/mainboard/ocp/tiogapass/Kconfig
M src/mainboard/ocp/tiogapass/devicetree.cb
M src/mainboard/ocp/tiogapass/dsdt.asl
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/Makefile.inc
R src/soc/intel/xeon_sp/bootblock.c
R src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/lpc.c
M src/soc/intel/xeon_sp/romstage.c
A src/soc/intel/xeon_sp/skx/Kconfig
A src/soc/intel/xeon_sp/skx/Makefile.inc
R src/soc/intel/xeon_sp/skx/acpi.c
R src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl
R src/soc/intel/xeon_sp/skx/acpi/iiostack.asl
R src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl
R src/soc/intel/xeon_sp/skx/acpi/uncore.asl
R src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl
R src/soc/intel/xeon_sp/skx/chip.c
R src/soc/intel/xeon_sp/skx/chip.h
R src/soc/intel/xeon_sp/skx/cpu.c
R src/soc/intel/xeon_sp/skx/hob_display.c
R src/soc/intel/xeon_sp/skx/include/soc/acpi.h
R src/soc/intel/xeon_sp/skx/include/soc/cpu.h
R src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h
R src/soc/intel/xeon_sp/skx/include/soc/irq.h
R src/soc/intel/xeon_sp/skx/include/soc/msr.h
R src/soc/intel/xeon_sp/skx/include/soc/nvs.h
R src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
R src/soc/intel/xeon_sp/skx/include/soc/ramstage.h
A src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
A src/soc/intel/xeon_sp/skx/romstage.c
R src/soc/intel/xeon_sp/skx/soc_util.c
R src/soc/intel/xeon_sp/skx/upd_display.c
M src/soc/intel/xeon_sp/uncore.c
A src/soc/intel/xeon_sp/util.c
35 files changed, 269 insertions(+), 190 deletions(-)