Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Karthik Ramasubramanian, Felix Held.
Raul Rangel uploaded patch set #5 to this change.
soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA
AMD platforms require the destination buffer to be 64 byte aligned
when using the SPI DMA controller.
BUG=b:179699789
TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug
$1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0}
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec
---
M src/soc/amd/common/block/lpc/Kconfig
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/58707/5
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