Srinidhi N Kaushik would like Hannah Williams to review this change.
acpi/cnvi.asl: Add _PRW for CNVi
Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
---
A src/soc/intel/apollolake/acpi/cnvi.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/include/soc/gpe.h
3 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22639/1
diff --git a/src/soc/intel/apollolake/acpi/cnvi.asl b/src/soc/intel/apollolake/acpi/cnvi.asl
new file mode 100644
index 0000000..5d3616c
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/cnvi.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* CNVi Controller 0:C.0 */
+Device (CNVI) {
+ Name(_ADR, 0x000C0000)
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 })
+
+ Method (_STA, 0)
+ {
+ Return (0xF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 97a25a2..5b8f9b7 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -56,4 +56,10 @@
/* SGX */
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
#include <soc/intel/common/acpi/sgx.asl>
+
+/* CNVi */
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "cnvi.asl"
+#endif
+
#endif
diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h
index 7dfb6f5..eb6e31f 100644
--- a/src/soc/intel/apollolake/include/soc/gpe.h
+++ b/src/soc/intel/apollolake/include/soc/gpe.h
@@ -33,6 +33,7 @@
#define GPE0A_GPIO_TIER1_SCI_STS 15
#define GPE0A_SMB_WAK_STS 16
#define GPE0A_SATA_PME_STS 17
+#define GPE0A_CNVI_PME_STS 18
/* Group DW0 is reserved in Apollolake */
To view, visit change 22639. To unsubscribe, visit settings.